Minimizing the Amount of Time Stamp Information Reported With Instrumentation Data

Abstract

This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined number of least significant bits overlapping a predetermined number of most significant bits. Each client receives the least significant bits. Each client associates captured data with a corresponding set of the least significant bits in a message. A central scheduling unit associates most significant bits of the time stamp value with the least significant bits of the message. This associating compares overlap bits of the most significant bits and least significant bits. The most significant bits are decremented until the overlap bits are equal.

What is claimed is: 
     
         1 . A time stamping subsystem of an electronic apparatus comprising:
 a time stamp generator generating a time stamp value having a first predetermined plural number of bits;   a first data bus connected to said timestamp generator having a second predetermined number of data lines transmitting in parallel said least significant bits of said time stamp value;   a second data bus connected to said time stamp generator having a third predetermined number of data lines transmitting in parallel said most significant bits of said time stamp value, said least significant bits of said first data bus overlapping said most significant bits of said second data bus;   at least one client, each client connected to said first data bus receiving said least significant bits of said time stamp value, each client capturing data from the electronic apparatus and associating said captured data with a corresponding set of said least significant bits of said time stamp value in a message;   a central scheduling unit connected to said second data bus and to each of said at least one client, said central scheduling unit receiving a message from said at least one client and associating most significant bits of said time stamp value from said second data bus with said least significant bits of said time stamp value of said message.   
     
     
         2 . The electronic apparatus of  claim 1 , wherein:
 said central scheduling unit includes
 a time stamp most significant bits register having an input connected to said second data bus, a first output for most significant bits, a second output for overlap bits and a decrement input, said time stamp most significant bits register decrementing data stored therein in response to an active decrement input, 
 a time stamp least significant bits register having an input connected to said at least one client receiving said least significant bits of said time stamp value associated with a message, a first output for overlap bits and a second output for least significant bits, 
 a comparator having a first input receiving said overlap bits of said time stamp most significant bits register, a second input receiving said overlap bits of said time stamp least significant bits register and an output indicating whether said inputs are equal, said output connected to said decrement input of said time stamp value most significant bits register, and 
 a time stamp value register having a first input connected to said first output of said time stamp most significant bits register, a second input receiving said overlap bits, a third input connected to said second output of said time stamp LSBs register and a load input connected to said output of said comparator. 
   
     
     
         3 . The electronic apparatus of  claim 2 , wherein:
 said time stamp most significant bits register decrements data stored therein when said comparator output indicates not equal; and   said time stamp value register loads data at said first, second and third inputs when said comparator output indicates equal.   
     
     
         4 . The electronic apparatus of  claim 2 , wherein:
 said second input of said time stamp value register is connected to said first output of said time stamp least significant bits register.   
     
     
         5 . A method of time stamping comprising the steps of:
 generating a time stamp value having a first predetermined plural number of bits;   transmitting least significant bits of said time stamp value to a client;   client capturing data from an electronic apparatus and associating said captured data with a corresponding set of said least significant bits of said time stamp value in a message;   associating most significant bits of said time stamp value with said least significant bits of said time stamp value of said message.   
     
     
         6 . The method of  claim 5 , wherein:
 said step of associating most significant bits of said time stamp value with said least significant bits of said time stamp value of said message includes
 capturing said time stamp most significant bits register having an overlap with said time stamp least significant bits, 
 comparing overlap bits of said time stamp most significant bits with overlap bits of said time stamp least significant bits, 
 decrementing said captures time stamp most significant bits when overlap bits are not equal, and 
 capturing said time stamp most significant bits, said overlap bits and said time stamp least significant bits when said overlap bits are equal.