SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF

Abstract

The present application provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

What is claimed: 
     
         1 . A device comprising:
 a semiconductor layer including silicon carbide;   a gate oxide layer disposed on the semiconductor layer;   a gate electrode including silicon disposed on the gate oxide layer, the gate electrode having a long dimension;   wherein said gate electrode is configured to electrically contact a gate voltage source such that currents through the gate electrode that are induced by the voltage source are directed substantially transverse to the long dimension of the gate electrode.   
     
     
         2 . The device of  claim 1 , wherein said gate oxide layer includes at least one of silicon dioxide, silicon nitride, or glass forming material. 
     
     
         3 . The device of  claim 1 , wherein said gate electrode includes polysilicon. 
     
     
         4 . The device of  claim 1 , further comprising a conductive layer on the gate electrode, the conductive layer being configured to electrically contact a gate voltage source so as to establish electrical contact between the gate voltage source and said gate electrode. 
     
     
         5 . The device of  claim 4 , wherein said conductive layer includes at least one of a metal layer, a metal silicide layer, or adjacent metal and metal silicide layers. 
     
     
         6 . The device of  claim 4 , wherein said conductive layer includes a metal silicide layer selected from the group consisting of tantalum silicide, nickel silicide, cobalt silicide, titanium silicide, molybdenum silicide, tungsten silicide, niobium silicide, hafnium silicide, zirconium silicide, vanadium silicide, chromium silicide, and platinum silicide. 
     
     
         7 . The device of  claim 4 , wherein said conductive layer includes at least one of tantalum, nickel, cobalt, titanium, molybdenum, tungsten, niobium, hafnium, zirconium, vanadium, chromium, or platinum. 
     
     
         8 . The device of  claim 4 , wherein said conductive layer extends substantially along the long dimension of the gate electrode.