Semiconductor package

Abstract

The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least on opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a substrate comprising a top surface, a pad, an anti-oxidation layer, and a solder mask, wherein the pad is disposed adjacent to the top surface of the substrate, the solder mask overlies and directly contacts a part of the pad and defines a solder mask opening so as to expose a remaining part of the pad, and the anti-oxidation layer is disposed over the remaining part of the pad exposed by the solder mask opening;   a chip mounted on the substrate;   a plurality of conductive elements electrically connecting the chip and the substrate;   a conductor disposed over the anti-oxidation layer; and   a molding compound disposed over the top surface of the substrate, wherein the molding compound comprises a first top surface and a second top surface, a first height of the first top surface of the molding compound is different from a second height of the second top surface of the molding compound, and a top end of the conductor is exposed adjacent to the second top surface of the molding compound.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the anti-oxidation layer is a plating layer. 
     
     
         3 . The semiconductor package of  claim 2 , wherein a width of the plating layer is smaller than a width of the pad. 
     
     
         4 . The semiconductor package of  claim 1 , wherein the conductor is a solder ball having a hemispherical shape. 
     
     
         5 . The semiconductor package of  claim 1 , wherein the first top surface of the molding compound overlies the chip and the conductive elements, and the first height is greater than the second height. 
     
     
         6 . The semiconductor package of  claim 1 , wherein the top end of the conductor is substantially coplanar with the second top surface of the molding compound. 
     
     
         7 . The semiconductor package of  claim 1 , wherein the pad comprises copper. 
     
     
         8 . A semiconductor package, comprising:
 a substrate comprising a top surface, a pad, and a solder mask, wherein the pad is disposed adjacent to the top surface of the substrate, and the solder mask defines a solder mask opening that partially exposes the pad to define a covered portion and an uncovered portion of the pad;   a conductor disposed over the uncovered portion of the pad; and   a molding compound disposed over the top surface of the substrate, wherein the molding compound comprises a first top surface and a second top surface, the second top surface of the molding compound is recessed below the first top surface of the molding compound, and a top end of the conductor is exposed adjacent to the second top surface of the molding compound.   
     
     
         9 . The semiconductor package of  claim 8 , wherein the solder mask directly contacts the covered portion of the pad. 
     
     
         10 . The semiconductor package of  claim 8 , wherein the covered portion of the pad is adjacent to a periphery of the pad. 
     
     
         11 . The semiconductor package of  claim 8 , wherein the substrate further comprises an anti-oxidation layer disposed over the uncovered portion of the pad. 
     
     
         12 . The semiconductor package of  claim 11 , wherein the anti-oxidation layer is inwardly recessed from a periphery of the pad. 
     
     
         13 . The semiconductor package of  claim 11 , wherein a top surface of the anti-oxidation layer is recessed below a top surface of the solder mask. 
     
     
         14 . The semiconductor package of  claim 8 , wherein a width of the solder mask opening at a top surface of the solder mask is substantially the same as a width of the solder mask opening adjacent to the pad. 
     
     
         15 . A semiconductor package, comprising:
 a substrate comprising a top surface, a pad, and an anti-oxidation layer, wherein the pad is disposed adjacent to the top surface of the substrate, and the anti-oxidation layer is disposed over a central part of the pad while a peripheral part of the pad is exposed by the anti-oxidation layer;   a chip disposed over the top surface of the substrate;   a conductor disposed over the anti-oxidation layer; and   a molding compound disposed over the top surface of the substrate, wherein the molding compound comprises a first top surface and a second top surface, the second top surface of the molding compound is recessed below the first top surface of the molding compound, and a top end of the conductor is exposed adjacent to the second top surface of the molding compound.   
     
     
         16 . The semiconductor package of  claim 15 , wherein the substrate further comprises a solder mask disposed adjacent to the top surface of the substrate, and the solder mask directly contacts the peripheral part of the pad. 
     
     
         17 . The semiconductor package of  claim 16 , wherein the solder mask defines a solder mask opening that exposes the anti-oxidation layer. 
     
     
         18 . The semiconductor package of  claim 16 , wherein a top surface of the anti-oxidation layer is recessed below a top surface of the solder mask. 
     
     
         19 . The semiconductor package of  claim 15 , wherein the anti-oxidation layer is a plating layer that comprises at least one of gold and nickel. 
     
     
         20 . The semiconductor package of  claim 15 , wherein the top end of the conductor is substantially coplanar with the second top surface of the molding compound.