Semiconductor chip and stacked semiconductor package having the same

Abstract

A semiconductor chip includes a substrate, through-electrodes passing through the substrate, and a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure.

What is claimed is: 
     
         1 . A semiconductor chip comprising:
 a substrate;   through-electrodes passing through the substrate; and   a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure.   
     
     
         2 . The semiconductor chip according to  claim 1 , wherein the dielectric layer with the dielectric constant decreasing structure comprises a hollow type dielectric layer which has an air gap defined in a center portion thereof. 
     
     
         3 . The semiconductor chip according to  claim 2 , wherein material comprising the hollow type dielectric layer includes any one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, polyimide, BCB (benzocyclobutene) and parylene. 
     
     
         4 . The semiconductor chip according to  claim 1 , wherein the dielectric layer with the dielectric constant decreasing structure comprises a porous dielectric layer which has a plurality of air gaps therein. 
     
     
         5 . The semiconductor chip according to  claim 4 , wherein material comprising the porous dielectric layer includes any one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, HSSQ (hydro silsesquioxane) and MSSQ (methyl silsesquioxane). 
     
     
         6 . The semiconductor chip according to  claim 1 , wherein the dielectric layer with the dielectric constant decreasing structure comprises a double-layered structure of a hollow type dielectric layer which has an air gap defined in the center portion thereof and an air gap-free dielectric layer which has no air gap therein. 
     
     
         7 . The semiconductor chip according to  claim 6 , wherein the hollow type dielectric layer and the air gap-free dielectric layer is include any one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, polyimide, BCB and parylene. 
     
     
         8 . The semiconductor chip according to  claim 1 , wherein the dielectric layer with the dielectric constant decreasing structure comprises a double-layered structure of a porous dielectric layer which has a plurality of air gaps therein and an air gap-free dielectric layer which has no air gap therein. 
     
     
         9 . The semiconductor chip according to  claim 8 , wherein material comprising the porous dielectric layer includes any one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, HSSQ and MSSQ. 
     
     
         10 . The semiconductor chip according to  claim 8 , wherein material comprising the air gap-free dielectric layer includes any one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, polyimide, BCB and to parylene. 
     
     
         11 . The semiconductor chip according to  claim 1 , wherein the dielectric layer with the dielectric constant decreasing structure comprises a double-layered structure of a hollow type dielectric is layer which has an air gap defined in the center portion thereof and a porous dielectric layer which has a plurality of air gaps therein. 
     
     
         12 . The semiconductor chip according to  claim 11 , wherein material comprising the hollow type dielectric layer includes any one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, polyimide, BCB and parylene. 
     
     
         13 . The semiconductor chip according to  claim 11 , wherein material comprising the porous dielectric layer includes any one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, HSSQ and MSSQ. 
     
     
         14 . A stacked semiconductor package comprising:
 a plurality of semiconductor chips each including a substrate, through-electrodes passing through the substrate and a dielectric layer formed between the substrate and the through-electrodes and having a dielectric constant decreasing structure, and stacked such that through-electrodes of the plurality of semiconductor chips are connected with one another.   
     
     
         15 . The stacked semiconductor package according to  claim 14 , further comprising:
 is a first dielectric layer formed under a lowermost semiconductor chip among the plurality of stacked semiconductor chips in such a way as to leave the through-electrodes of the lowermost semiconductor chip exposed;   redistribution lines formed under the first dielectric layer and electrically connected with the exposed through-electrodes of the lowermost semiconductor chip; and   a second dielectric layer formed under the first dielectric layer including the redistribution lines in such a way as to leave portions of the redistribution lines exposed.   
     
     
         16 . The stacked semiconductor package according to  claim 15 , further comprising:
 external connection terminals mounted to the portions of the redistribution lines which are exposed through the second dielectric layer.   
     
     
         17 . The stacked semiconductor package according to  claim 14 , further comprising:
 a structural body supporting the semiconductor chips and having connection electrodes which are electrically connected with the through-electrodes of the lowermost semiconductor chip among the plurality of stacked semiconductor chips.   
     
     
         18 . The stacked semiconductor package according to  claim 17 , wherein the structural body comprises any one of a printed circuit board, an interposer and a semiconductor package. 
     
     
         19 . The stacked semiconductor package according to  claim 14 , wherein the dielectric layer with the dielectric constant decreasing structure of the lowermost semiconductor chip has a highest dielectric constant among the semiconductor chips, dielectric constants of dielectric layers with the dielectric constant decreasing structure gradually decrease toward an uppermost semiconductor chip, and the dielectric layer with the dielectric constant decreasing structure of the uppermost semiconductor chip has a lowest dielectric constant. 
     
     
         20 . The stacked semiconductor package according to  claim 19 ,
 wherein the semiconductor chips include a first semiconductor chip, a second semiconductor chip which is stacked under the first semiconductor chip, and a third semiconductor chip which is stacked under the second semiconductor chip, and   wherein the dielectric layer of the third semiconductor chip comprises a double-layered structure of a porous dielectric layer which has a plurality of air gaps therein and an air gap-free dielectric layer which has no air gap therein, the dielectric layer of is the second semiconductor chip comprises a single-layered structure of a porous dielectric layer which has a plurality of air gaps therein, and the dielectric layer of the first semiconductor chip comprises a single-layered structure of a hollow type dielectric layer which has an air gap defined in a center portion thereof.