Silicon-on-insulator transistor with self-aligned borderless source/drain contacts

Abstract

A transistor includes a semiconductor layer, a gate spacer on the semiconductor layer, a gate dielectric comprising a first portion above the semiconductor layer and a second portion on sidewalls of the gate spacer, a work function metal layer comprising a first portion on the first portion of the gate dielectric and a second portion on sidewalls of the gate dielectric, a gate conductor on the first portion of the work function layer and abutting the second portion of the work function layer, a dielectric layer on the semiconductor layer and abutting the gate spacer, an oxide film above only one of the work function layer and the gate conductor, an oxide cap, source/drain regions, and a source/drain contact passing through the dielectric layer and contacting an upper surface of one of the source/drain regions. A portion of the source/drain contact is located directly on the oxide cap.

1 - 9 . (canceled) 
     
     
         10 . A transistor comprising:
 a semiconductor layer;   a gate spacer located directly on the semiconductor layer;   a U-shaped gate dielectric comprising a horizontal portion located directly on the semiconductor layer and a vertical portion located on vertical sidewalls of the gate spacer, an upper surface of the gate spacer being co-planar with an upper surface of the vertical portion of the gate dielectric;   a U-shaped work function metal layer comprising a horizontal portion located directly on the horizontal portion of the gate dielectric and a vertical portion located on vertical sidewalls of the vertical portion of the gate dielectric;   a gate conductor comprising a conductive material, the gate conductor being located directly on the horizontal portion of the work function metal layer and abutting vertical sidewalls of the vertical portion of the work function metal layer;   a dielectric layer located on the semiconductor layer and abutting the gate spacer;   an oxide film located directly on one and only one of the work function metal layer and the gate conductor, an upper surface of the dielectric layer being co-planar with an upper surface of the oxide film and the upper surface of the vertical portion of the gate dielectric;   an oxide cap located directly on the upper surface of the vertical portion of the gate dielectric, the upper surface of the oxide film, and a portion of the upper surface of the dielectric layer;   source/drain regions located in the semiconductor layer; and   a source/drain contact passing through the dielectric layer and contacting an upper surface of one of the source/drain regions, a portion of the source/drain contact being located directly on the oxide cap.   
     
     
         11 . The transistor of  claim 10 , further comprising:
 a substrate; and   a buried insulator layer above the substrate, the semiconductor layer being located on the buried insulator layer.   
     
     
         12 . The transistor of  claim 10 ,
 wherein the oxide film is located directly on the gate conductor and is not located directly on the work function metal layer,   the oxide cap is also located directly on an upper surface of the vertical portion of the work function metal layer, and   the upper surface of the vertical portion of the work function metal layer is also co-planar with the upper surface of the dielectric layer.   
     
     
         13 . The transistor of  claim 10 ,
 wherein the oxide film is located directly on the work function metal layer and is not located directly on the gate conductor,   the oxide cap is also located directly on an upper surface of the gate conductor, and   the upper surface of the gate conductor is also co-planar with the upper surface of the dielectric layer.   
     
     
         14 . The transistor of  claim 10 , further comprising an interlayer dielectric located on the dielectric layer and the oxide cap. 
     
     
         15 . The transistor of  claim 14 , wherein the oxide film is composed of silicon oxide, the oxide cap is composed of silicon oxide, and the interlayer dielectric is composed of silicon nitride. 
     
     
         16 . The transistor of  claim 10 , wherein a lateral extent of the oxide cap is greater than a lateral extent of the gate spacer. 
     
     
         17 . The transistor of  claim 10 , wherein the oxide film has a thickness of less than about 8 nm. 
     
     
         18 . The transistor of  claim 10 , wherein the oxide film has a thickness of about 5-10 nm. 
     
     
         19 . An integrated circuit comprising a plurality of transistors, at least one of the transistors comprising:
 a semiconductor layer;   a gate spacer located directly on the semiconductor layer;   a U-shaped gate dielectric comprising a horizontal portion located directly on the semiconductor layer and a vertical portion located on vertical sidewalls of the gate spacer, an upper surface of the gate spacer being co-planar with an upper surface of the vertical portion of the gate dielectric;   a U-shaped work function metal layer comprising a horizontal portion located directly on the horizontal portion of the gate dielectric and a vertical portion located on vertical sidewalls of the vertical portion of the gate dielectric;   a gate conductor comprising a conductive material, the gate conductor being located directly on the horizontal portion of the work function metal layer and abutting vertical sidewalls of the vertical portion of the work function metal layer;   a dielectric layer located on the semiconductor layer and abutting the gate spacer;   an oxide film located directly on one and only one of the work function metal layer and the gate conductor, an upper surface of the dielectric layer being co-planar with an upper surface of the oxide film and the upper surface of the vertical portion of the gate dielectric;   an oxide cap located directly on the upper surface of the vertical portion of the gate dielectric, the upper surface of the oxide film, and a portion of the upper surface of the dielectric layer;   source/drain regions located in the semiconductor layer; and   a source/drain contact passing through the dielectric layer and contacting an upper surface of one of the source/drain regions, a portion of the source/drain contact being located directly on the oxide cap.   
     
     
         20 . The integrated circuit of  claim 19 ,
 wherein the oxide film is located directly on the gate conductor and is not located directly on the work function metal layer,   the oxide cap is also located directly on an upper surface of the vertical portion of the work function metal layer, and   the upper surface of the vertical portion of the work function metal layer is also co-planar with the upper surface of the dielectric layer.   
     
     
         21 . The integrated circuit of  claim 19 ,
 wherein the oxide film is located directly on the work function metal layer and is not located directly on the gate conductor,   the oxide cap is also located directly on an upper surface of the gate conductor, and   the upper surface of the gate conductor is also co-planar with the upper surface of the dielectric layer.   
     
     
         22 . The integrated circuit of  claim 19 , wherein the at least one transistor further comprises:
 an interlayer dielectric located on the dielectric layer and the oxide cap,   wherein the oxide film is composed of silicon oxide, the oxide cap is composed of silicon oxide, and the interlayer dielectric is composed of silicon nitride.   
     
     
         23 . The integrated circuit of  claim 19 , wherein the oxide film has a thickness of less than about 10 nm. 
     
     
         24 . The transistor of  claim 10 , wherein no portion of the oxide cap is located below the upper surface of the oxide film. 
     
     
         25 . The transistor of  claim 10 , wherein the oxide cap is located above all of the U-shaped gate dielectric and all of the U-shaped work function metal layer. 
     
     
         26 . The transistor of  claim 10 , wherein the oxide cap extends beyond outer edges of the gate spacer so that a combination of the oxide cap and the gate spacer encapsulates a gate stack comprising the U-shaped gate dielectric, the U-shaped work function metal layer, and the gate conductor. 
     
     
         27 . The transistor of  claim 10 , wherein all of the oxide cap is located above a gate stack comprising the U-shaped gate dielectric, the U-shaped work function metal layer, and the gate conductor. 
     
     
         28 . The integrated circuit of  claim 19 , wherein the oxide cap extends beyond outer edges of the gate spacer so that a combination of the oxide cap and the gate spacer encapsulates a gate stack comprising the U-shaped gate dielectric, the U-shaped work function metal layer, and the gate conductor. 
     
     
         29 . The integrated circuit of  claim 19 , wherein all of the oxide cap is located above a gate stack comprising the U-shaped gate dielectric, the U-shaped work function metal layer, and the gate conductor.