Methods and Apparatus for Thinner Package on Package Structures

Abstract

Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

What is claimed is: 
     
         1 . A semiconductor device structure, comprising:
 a first integrated circuit package comprising at least one integrated circuit device mounted on a first substrate, and having a plurality of package on package connectors extending from a bottom surface of the first substrate; and   a second integrated circuit package comprising at least another integrated circuit device mounted on a second substrate, comprising a plurality of lands on an upper surface of the second substrate coupled to the plurality of package on package connectors, and comprising a plurality of external connectors extending from a second bottom surface of the second integrated circuit package;   wherein at least the second substrate comprises a plurality of dielectric layers and conductors stacked together without an intervening core.   
     
     
         2 . The semiconductor device structure of  claim 1 , wherein the plurality of package on package connectors are solder. 
     
     
         3 . The semiconductor device structure of  claim 1 , wherein the plurality of external connectors are solder. 
     
     
         4 . The semiconductor device structure of  claim 1 , wherein the first substrate comprises a plurality of dielectric layers and conductors stacked together without an intervening core. 
     
     
         5 . The semiconductor device structure of  claim 1 , wherein the first substrate comprises a first plurality of dielectric layers on a first surface of a core material, and a second plurality of dielectric layers on a second surface of the core material. 
     
     
         6 . The semiconductor device structure of  claim 5 , wherein the first substrate further comprises a cavity formed in a central portion of the bottom surface of the first substrate. 
     
     
         7 . The semiconductor device structure of  claim 6 , wherein the at least another integrated circuit device of the second package extends partially into the cavity formed in the central portion of the bottom surface of the first surface. 
     
     
         8 . The semiconductor device structure of  claim 1 , wherein the at least another integrated circuit device is embedded into the second substrate. 
     
     
         9 . The semiconductor device structure of  claim 1 , wherein the at least another integrated circuit device is mounted to the second substrate using board on trace connectors. 
     
     
         10 . The semiconductor device structure of  claim 1 , wherein the at least one integrated circuit device is a memory. 
     
     
         11 . The semiconductor device structure of  claim 1 , wherein the at least another integrated circuit device is a microprocessor. 
     
     
         12 . A semiconductor device structure, comprising:
 a first integrated circuit package comprising at least one integrated circuit device mounted on a first substrate, and having a plurality of package on package connectors extending from a bottom surface of the first substrate, and a cavity formed on the bottom surface and extending into the first substrate, the package on package connectors arranged spaced from the cavity; and   a second integrated circuit package comprising at least another integrated circuit device mounted on a second substrate, comprising a plurality of lands on an upper surface of the second substrate coupled to the plurality of package on package connectors, and further comprising a plurality of external connectors extending from a bottom surface of the second integrated circuit package;   wherein at least a portion of the at least another integrated circuit device extends into the cavity on the bottom surface of the first substrate.   
     
     
         13 . The semiconductor device structure of  claim 12 , wherein the second substrate comprises a plurality of dielectric layers and conductors stacked together without an intervening core. 
     
     
         14 . The semiconductor device structure of  claim 12 , wherein the first substrate comprises a first plurality of dielectric layers on a first surface of a core material, and a second plurality of dielectric layers on a second surface of the core material. 
     
     
         15 . The semiconductor device structure of  claim 14 , wherein the second substrate comprises a third plurality of dielectric layers on a first surface of a second core material, and a fourth plurality of dielectric layers on a second surface of the second core material. 
     
     
         16 . A method, comprising:
 providing a first integrated circuit package comprising one or more integrated circuits on an upper surface of a first substrate, and providing a plurality of package on package connectors extending from a lower surface of the first substrate;   providing a second integrated circuit package comprising providing a second substrate having one or more other integrated circuits on an upper surface of the second substrate, the second substrate comprising a plurality of lands on the upper surface of the second substrate arranged for receiving the plurality of package on package connectors, and further comprising providing a plurality of external connectors extending from a bottom surface of the second substrate; and   mounting the first integrated circuit package to the upper surface of the second substrate by bonding the package on package connectors of the first integrated circuit package to the plurality of lands on the second substrate;   wherein providing the second substrate comprises providing a plurality of dielectric layers and conductors stacked over one another without an intervening core.   
     
     
         17 . The method of  claim 16 , wherein providing the second substrate further comprises:
 providing a first dielectric layer with a conductor covering one surface;   forming first level vias in the first dielectric layer;   forming first level conductive material in the first level vias;   forming first level conductive traces over the conductive material in the first level vias; and   disposing a second dielectric layer over the conductive traces.   
     
     
         18 . The method of  claim 17  and further comprising:
 forming second level vias in the second dielectric layer; 
 forming conductive material in the second level vias in the second dielectric layer; 
 forming second level conductive traces over the conductive material in the second level vias; and 
 patterning the conductor covering the one surface for receiving external connectors. 
 
     
     
         19 . The method of  claim 18  and further comprising flip chip mounting the one or more integrated circuits to the second level conductive traces of the second substrate. 
     
     
         20 . The method of  claim 16 , and further comprising embedding the one or more integrated circuits into the second substrate.