Low Cost and High Performance Flip Chip Package

Abstract

A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.

1 . A semiconductor package comprising:
 a heat spreader having a recess;   a semiconductor die situated in said recess and attached to said heat spreader, said semiconductor die having a plurality of die contact pads;   a package substrate comprising at least one laminate dielectric film;   a plurality of vias within said at least one laminate dielectric film for connecting said plurality of die contact pads to a corresponding plurality of package contact pads.   
     
     
         2 . The semiconductor package of  claim 1 , wherein said semiconductor die is a flip chip including said plurality of die contact pads and having no flip chip solder bumps. 
     
     
         3 . The semiconductor package of  claim 2  wherein said plurality of vias are directly connected to said plurality of die contact pads. 
     
     
         4 . The semiconductor package of  claim 1 , wherein said package substrate is coreless. 
     
     
         5 . The semiconductor package of  claim 1 , wherein said semiconductor die is attached to said heat spreader by adhesive thermal interface material (TIM). 
     
     
         6 . The semiconductor package of  claim 1 , wherein said at least one laminate dielectric film is an Ajinomoto Build-up Film (ABF). 
     
     
         7 . A semiconductor package comprising:
 a heat spreader having a recess;   a semiconductor die situated in said recess and attached to said heat spreader, said semiconductor die having a plurality of die contact pads;   a package substrate comprising a stack of laminate dielectric films;   a plurality of electrical connection routes within said stack of laminate dielectric films for connecting said plurality of die contact pads to a corresponding plurality of package contact pads.   
     
     
         8 . The semiconductor package of  claim 7 , wherein said semiconductor die is a flip chip including said plurality of die contact pads and having no flip chip solder bumps. 
     
     
         9 . The semiconductor package of  claim 8 , wherein a plurality of vias in a lower laminate dielectric film in said stack of laminate dielectric films are directly connected to said plurality of die contact pads. 
     
     
         10 . The semiconductor package of  claim 8 , wherein said package substrate is coreless. 
     
     
         11 . The semiconductor package of  claim 8 , wherein said semiconductor die is attached to said heat spreader by adhesive thermal interface material (TIM). 
     
     
         12 - 20 . (canceled)