Dislocation smt for finfet device

Abstract

A method for performing a stress memorization technique (SMT) a FinFET and a FinFET having memorized stress effects including multi-planar dislocations are disclosed. An exemplary embodiment includes receiving a FinFET precursor with a substrate, a fin structure on the substrate, an isolation region between the fin structures, and a gate stack over a portion of the fin structure. The gate stack separates a source region of the fin structure from a drain region of the fin structure and creates a gate region between the two. The embodiment also includes forming a stress-memorization technique (SMT) capping layer over at least a portion of each of the fin structures, isolation regions, and the gate stack, performing a pre-amorphization implant on the FinFET precursor by implanting an energetic doping species, performing an annealing process on the FinFET precursor, and removing the SMT capping layer.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device comprising:
 receiving a FinFET precursor comprising:
 a substrate; 
 a fin structure formed on the substrate; 
 an isolation region formed on the substrate and isolating the fin structure; and 
 a gate stack formed over a portion of the fin structure, thereby separating a source region of the fin structure from a drain region of the fin structure and creating a gate region of the fin structure therebetween; 
   forming a stress-memorization technique (SMT) capping layer over at least a portion of each of the fin structure, the isolation region, and the gate stack;   performing a pre-amorphization implant on the FinFET precursor by implanting an energetic doping species;   performing an annealing process on the FinFET precursor; and   removing the SMT capping layer.   
     
     
         2 . The method of  claim 1 , the method further comprising:
 removing a portion of the fin structure; and   thereafter forming a secondary source/drain region on top of the fin structure.   
     
     
         3 . The method of  claim 2 , wherein the removing the portion of the fin structure is performed to a specific depth, and wherein the specific depth is selected to control the presence of stress effects in the secondary source/drain region. 
     
     
         4 . The method of  claim 1 , the method further comprising performing a manufacturing process on the FinFET precursor following removing the SMT capping layer. 
     
     
         5 . A semiconductor device comprising:
 a substrate having a surface;   a fin structure formed over the surface of the substrate, the fin structure having an elongated body, a longitudinal axis, and a transverse axis parallel to the surface of the substrate, wherein the fin structure has a dislocation;   an isolation region formed on the surface of the substrate and isolating the fin structure; and   a gate stack formed over a portion of the fin structure, thereby separating a source region of the fin structure and a drain region of the fin structure and creating gate region of the fin structure therebetween.   
     
     
         6 . The semiconductor device of  claim 5 , wherein:
 the dislocation is a first dislocation;   the semiconductor device further comprises a second dislocation formed within the fin structure; and   the first dislocation and the second dislocation are not coplanar.   
     
     
         7 . The semiconductor device of  claim 5 , wherein the dislocation is parallel to the surface of the substrate. 
     
     
         8 . The semiconductor device of  claim 5 , wherein the dislocation is parallel to the longitudinal axis of the corresponding fin structure and extends in the direction of the substrate. 
     
     
         9 . The semiconductor device of  claim 5 , wherein the dislocation is parallel to the transverse axis of the corresponding fin structure and extends in the direction of the substrate. 
     
     
         10 . The semiconductor device of  claim 5 , wherein the fin structure comprises a first fin portion and a second fin portion and wherein the second fin portion is a secondary source/drain region. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the dislocation is formed entirely within the second fin portion. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the dislocation is formed within the first fin portion and the second fin portion. 
     
     
         13 . A semiconductor device comprising:
 a substrate having a surface;   an elevated device body formed over the surface of the substrate, the elevated device body comprising a drain region, a source region, and a gate region located between the drain and source regions, wherein the elevated device body has a longitudinal axis and a transverse axis parallel to the surface of the substrate;   a dislocation formed within the elevated device body;   an isolation region formed on the surface of the substrate and isolating the elevated device body; and   a gate stack formed over a portion of the gate region of the elevated device body.   
     
     
         14 . The semiconductor device of  claim 13 , wherein:
 the dislocation is a first dislocation;   the semiconductor device further comprises a second dislocation formed within the elevated device body;   the first dislocation and the second dislocation are formed within the same of the drain region, the source region, and the gate region of the elevated device body; and   the first dislocation and the second dislocation are not coplanar.   
     
     
         15 . The semiconductor device of  claim 13 , wherein the dislocation is parallel to the surface of the substrate. 
     
     
         16 . The semiconductor device of  claim 13 , wherein the dislocation is parallel to the longitudinal axis of the corresponding elevated device body and extends in the direction of the substrate. 
     
     
         17 . The semiconductor device of  claim 13 , wherein the dislocation is parallel to the transverse axis of the corresponding elevated device body and extends in the direction of the substrate. 
     
     
         18 . The semiconductor device of  claim 13 , wherein the dislocation is formed entirely within the source region of the elevated device body. 
     
     
         19 . The semiconductor device of  claim 13 , wherein the dislocation is formed entirely within the drain region of the elevated device body. 
     
     
         20 . The semiconductor device of  claim 13 , wherein the dislocation is formed within the gate region and one of the source region and the drain region of the elevated device body.