Memory device protection layer

Abstract

A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.

What is claimed is: 
     
         1 - 20 . (canceled) 
     
     
         21 . A device comprising:
 a memory device comprising:   a substrate,   a first dielectric layer formed over the substrate,   a charge storage layer formed over the first dielectric layer,   a second dielectric layer formed over the charge storage layer,   a control gate layer formed over the second dielectric layer,   a source region formed in the substrate,   a drain region formed in the substrate,   a protection layer formed on:
 a top surface of the source region, 
 a top surface of the drain region, and 
 side surfaces of the first dielectric layer, the charge storage layer, the second dielectric layer, and the control gate layer,
 the protection layer substantially contacting at least one of the first dielectric layer, the charge storage layer, the second dielectric layer, or the control gate layer, 
 
   spacers formed on the side surfaces of the first dielectric layer, the charge storage layer, the second dielectric layer, and the control gate layer, and   a third dielectric layer formed over the first dielectric layer, the charge storage layer, the second dielectric layer, the control gate layer, and the spacers,
 the third dielectric layer substantially contacting a portion of the spacers. 
   
     
     
         22 . The device of  claim 21 , where the device comprises at least one of a computer, a printer, a monitor, a camera, a calculator, a television, a stereo, a radio, a home entertainment system, an MP 3  player, a DVD player, a video game system, a radiotelephone handset, a personal communications system (PCS) terminal, a personal digital assistant (PDA), a global positioning system (GPS) receiver, an electronic sensor, an electronic instrument, an industrial control system, a network device, or an engine control system. 
     
     
         23 . The device of  claim 21 , where the protection layer includes a nitride or an oxinitride, and
 where a thickness of the protection layer ranges from about 50 Å to about 500 Å.   
     
     
         24 . The device of  claim 21 , where the spacers include a silicon oxide, a silicon nitride, a silicon oxynitride, and
 where the spacers are formed on the protection layer,
 the spacers substantially contacting the protection layer. 
   
     
     
         25 . The device of  claim 21 , where the protection layer at least one of minimizes or prevents non-uniform thickening of one or more of the first dielectric layer or the second dielectric layer. 
     
     
         26 . The device of  claim 21 , where the protection layer at least one of minimizes or prevents mobile ion penetration in the device from back end of line (BEOL) processing. 
     
     
         27 . The device of  claim 21 , where the protection layer includes a dielectric material that minimizes diffusion of oxygen, and
 where the protection layer at least one of minimizes or prevents formation of bird's beaks associated with the memory device.   
     
     
         28 . A semiconductor device comprising:
 a substrate;   a memory cell formed over the substrate,
 the memory cell comprising:
 a first dielectric layer formed over the substrate, 
 a charge storage layer formed over the first dielectric layer, 
 a second dielectric layer formed over the charge storage layer, and 
 a control gate layer formed over the second dielectric layer; 
 
   a layer formed over:
 a source region of the substrate, 
 a drain region of the substrate, and 
 the memory cell,
 the layer substantially contacting the source region, the drain region, and 
 
 the memory cell; 
   spacers formed, on the layer, adjacent side surfaces of the memory cell; and   a third dielectric layer formed over:
 the memory cell, and 
 the spacers, 
 the third dielectric layer substantially contacting a portion of the spacers. 
   
     
     
         29 . The semiconductor device of  claim 28 , where the layer prevents oxygen from oxidizing at least one of the substrate or a control gate electrode of the control gate layer, and
 where the layer at least one of minimizes or prevents formation of bird's beaks below the memory cell.   
     
     
         30 . The semiconductor device of  claim 28 , where the layer at least one of minimizes or prevents from oxidation-enhanced diffusion relating to the semiconductor device, and
 where the layer at least one of minimizes or prevents non-uniform thickening of one or more of the first dielectric layer or the second dielectric layer.   
     
     
         31 . The semiconductor device of  claim 28 , where the layer at least one of minimizes or prevents mobile ion penetration in the semiconductor device from back end of line (BEOL) processing. 
     
     
         32 . The semiconductor device of  claim 28 , where the layer includes a nitride or an oxinitride, and
 where a thickness of the layer ranges from about 50 Å to about 500 Å.   
     
     
         33 . The semiconductor device of  claim 28 , further comprising:
 a contact formed between the memory cell and another memory cell of the semiconductor device.   
     
     
         34 . A device comprising:
 a memory cell formed over a substrate,
 the memory cell comprising:
 a first dielectric layer formed over the substrate, 
 a charge storage layer formed over the first dielectric layer, 
 a second dielectric layer formed over the charge storage layer, and 
 a control gate layer formed over the second dielectric layer; 
 
   a layer formed on side surfaces of the memory cell,
 the layer contacting the side surfaces of the memory cell; 
   spacers formed, on the layer, adjacent the side surfaces of the memory cell,
 the spacers substantially contacting the layer; and 
   a third dielectric layer formed over:
 the memory cell, and 
 the spacers, 
 the third dielectric layer substantially contacting a portion of the spacers. 
   
     
     
         35 . The device of  claim 34 , further comprising:
 another memory cell,
 the third dielectric layer being formed over the other memory cell; and 
   a contact formed between the memory cell and the other memory cell.   
     
     
         36 . The device of  claim 34 , where the layer includes a nitride or an oxinitride, and
 where a thickness of the layer ranges from about 50 Å to about 150 Å.   
     
     
         37 . The device of  claim 34 , where the spacers include a silicon oxide, a silicon nitride, or a silicon oxynitride. 
     
     
         38 . The device of  claim 34 , where the layer prevents oxygen from oxidizing at least one of the substrate or a control gate electrode of the control gate layer, and
 where the layer at least one of minimizes or prevents formation of bird's beaks relating to the memory cell.   
     
     
         39 . The device of  claim 34 , where the layer at least one of minimizes or prevents oxidation-enhanced diffusion relating to the device, and
 where the layer at least one of minimizes or prevents non-uniform thickening of at least one of the first dielectric layer or the second dielectric layer.   
     
     
         40 . The device of  claim 34 , where the layer at least one of minimizes or prevents mobile ion penetration in the device from back end of line (BEOL) processing relating to the device.