Method of manufacturing coreless substrate having filled via pad

Abstract

A method of manufacturing a coreless substrate having filled via pads, including: forming a first insulating layer on one side of a carrier forming a build-up layer including a build-up insulating layer and a build-up circuit layer having a build-up via on the first insulating layer, and forming a second insulating layer on the build-up layer; removing the carrier, and forming via-holes in the first and second insulating layers; and conducting a filled plating process in the via-holes of the first and second insulating layers thus forming first and second filled via pads therein.

What is claimed is: 
     
         1 . A method of manufacturing a coreless substrate having filled via pads, comprising:
 forming a first insulating layer on one side of a carrier;   forming a build-up layer including a build-up insulating layer and a build-up circuit layer having a build-up via on the first insulating layer, and forming a second insulating layer on the build-up layer;   removing the carrier, and forming via-holes in the first and second insulating layers; and   conducting a filled plating process in the via-holes of the first and second insulating layers thus forming first and second filled via pads therein.   
     
     
         2 . The method according to  claim 1 , further comprising, after conducting the filled plating process, subjecting surfaces of the first and second filled via pads to an organic solderability preservative (OSP) treatment or a formation of an electroless nickel immersion gold (ENIG) layer thereon. 
     
     
         3 . The method according to  claim 1 , further comprising, after conducting the filled plating process, forming solder balls on the first and second filled via pads. 
     
     
         4 . The method according to  claim 1 , wherein the carrier comprises a copper clad laminate including an insulating resin layer and a thin copper layer formed on at least one side of the insulating resin layer, and a release layer disposed on the copper clad laminate. 
     
     
         5 . The method according to  claim 1 , wherein conducting the filled plating process comprises:
 forming seed layers on the first and second insulating layers including the via-holes;   applying a resist layer on the first and second insulating layers and patterning the resist layer to form openings through which the via-holes are exposed;   forming filled plating layers on the via-holes exposed through the openings;   eliminating the resist layers; and   eliminating the seed layers and the filled plating layers on the first and second insulating layers to form first and second filled via pads.   
     
     
         6 . The method according to  claim 5 , wherein, in forming seed layers, the seed layers are formed through an electroless plating process or a sputtering process. 
     
     
         7 . The method according to  claim 5 , wherein, eliminating the seed layers and the filled plating layers comprises eliminating the seed layers and the filled plating layers such that surfaces of the first and second filled via pads are flush with surfaces of the first and second insulating layers. 
     
     
         8 . The method according to  claim 1 , wherein the first and second filled via pads have shapes facing each other. 
     
     
         9 . The method according to  claim 1 , wherein the second filled via pads and the build-up via have shapes corresponding to each other.