Floating-point vector normalisation

Abstract

When performing vector normalisation upon floating point values, an approximate reciprocal value generating instruction is used to generate an approximate reciprocal value with a mantissa of one and an exponent given by a bitwise inversion of the exponent field of the input floating point number. A modified number of multiplication instruction is used which performs a multiplication giving the standard IEEE 754 results other than when a signed zero is multiplied by a signed infinity which results a signed predetermined substitute value, such as 2. The normalisation operation may be performed by calculating a scaling value in dependence upon the vector floating point value using the approximate reciprocal value generating instruction. Each of the input components may then be scaled using the modify multiplication instruction to generate a scaled vector floating point value formed of a plurality of scaled components. The magnitude of the scaled vector floating point value can then be calculated and each of the individual scaled components divided by this magnitude to generate a normalised vector floating point value. The scaling value may be set to 2, where C is an integer value selected such that the sum of the squares of the plurality of scale components is less than a predetermined limit value.

1 . Apparatus for processing data comprising:
 processing circuitry configured to perform processing operations upon data values; and   decoder circuitry coupled to said processing circuitry and configured to decode program instructions to generate control signals for controlling said processing circuitry to perform processing operations specified by said program instructions; wherein   said decoder circuitry decodes an approximate reciprocal value generating instruction to generate control signals to control said processing circuitry to perform a processing operation upon a floating point number with an integer exponent value E and a mantissa value M to generate an approximate reciprocal value with an exponent C that is dependent upon E and a mantissa that represents 1.   
     
     
         2 . Apparatus as claimed in  claim 1 , wherein C is −E. 
     
     
         3 . Apparatus as claimed in  claim 1 , wherein E is subject to a predetermined integer offset O, and C is a bitwise inversion of E. 
     
     
         4 . Apparatus for processing data comprising:
 processing means for performing processing operations upon data values; and   decoder means for decoding program instructions to generate control signals for controlling said processing circuitry to perform processing operations specified by said program instructions; wherein   said decoder means decodes an approximate reciprocal value generating instruction to generate control signals to control said processing means perform a processing operation upon a floating point number with an integer exponent value E and a mantissa value M to generate an approximate reciprocal value with an exponent C that is dependent upon E and a mantissa that represents 1.   
     
     
         5 . A method of processing data comprising the steps of:
 performing processing operations upon data values; and   decoding program instructions to generate control signals for controlling said processing operations specified by said program instructions; wherein   said decoding step decodes an approximate reciprocal value generating instruction to generate control signals to control said processing step to perform a processing operation upon a floating point number with an integer exponent value E and a mantissa value M to generate an approximate reciprocal value with an exponent C that is dependent upon E and a mantissa that represents 1.   
     
     
         6 . Apparatus for processing data comprising:
 processing circuitry configured to perform processing operations upon data values; and   decoder circuitry coupled to said processing circuitry and configured to decode program instructions to generate control signals for controlling said processing circuitry to perform processing operations specified by said program instructions; wherein   said decoder circuitry decodes a modified multiply instruction that has as input operands two floating point numbers to generate control signals to control said processing circuitry when one of said two floating point numbers is a signed zero value given by (−1) SZ *0, where SZ is a sign value of said signed zero value, and another of said two floating point numbers is a signed infinity value (−1) SI *∞, where SI is a sign value of said signed infinity value, to generate as a modified multiply result value a predetermined value given by (−1) (SZ+SI) *PSV, where PSV is a predetermined substitute value.   
     
     
         7 . Apparatus as claimed in  claim 6 , wherein said predetermined substitute value is 1. 
     
     
         8 . Apparatus as claimed in  claim 6 , wherein said predetermined substitute value is 2. 
     
     
         9 . Apparatus as claimed in any one of  claims 6  to  8 , wherein for other values of said two floating point numbers, said modified multiply value has a value in according with a floating point product of said two floating point numbers as specified by IEEE Standard 754. 
     
     
         10 . Apparatus as claimed in any one of  claims 6  to  9 , wherein said modified multiply instruction is a vector instruction operating upon a plurality of sets of input operands, each set of input operands being processed as specified for said two floating point numbers. 
     
     
         11 . Apparatus for processing data comprising:
 processing means for performing processing operations upon data values; and   decoder means for decoding program instructions to generate control signals for controlling said processing means to perform processing operations specified by said program instructions; wherein   said decoder means decodes a modified multiply instruction that has as input operands two floating point numbers to generate control signals to control said processing means when one of said two floating point numbers is a signed zero value given by (−1) SZ *0, where SZ is a sign value of said signed zero value, and another of said two floating point numbers is a signed infinity value (−1) SI *∞, where SI is a sign value of said signed infinity value, to generate as a modified multiply result value a predetermined value given by (−1) (SZ+SI) *PSV, where PSV is a predetermined substitute value.   
     
     
         12 . A method of data comprising the steps of:
 performing processing operations upon data values; and   decoding program instructions to generate control signals for controlling said processing operations specified by said program instructions; wherein   said decoding decodes a modified multiply instruction that has as input operands two floating point numbers to generate control signals to control said processing step when one of said two floating point numbers is a signed zero value given by (−1) SZ *0, where SZ is a sign value of said signed zero value, and another of said two floating point numbers is a signed infinity value (−1) SI *∞, where SI is a sign value of said signed infinity value, to generate as a modified multiply result value a predetermined value given by (−1) (SZ+SI) *PSV, where PSV is a predetermined substitute value.   
     
     
         13 . A method of operating a data processing apparatus to normalise a vector floating point value having a plurality of components, each of said plurality of components including an integer exponent value and a mantissa value, said method comprising the steps of:
 calculating a scaling value in dependence upon said vector floating point value;   scaling each of said plurality of components in dependence upon said scaling value to generate a scaled vector floating point value having a plurality of scaled components;   calculating a magnitude of said scaled vector floating point value; and   dividing each of said plurality of scaled components by said magnitude to generate a normalised vector floating point value; wherein   said step of calculating a scaling value generates a scaling value of 2 C , where C is an integer value selected such that a sum of squares of said plurality of scaled components is less than a predetermined limit value.   
     
     
         14 . A method as claimed in  claim 13 , wherein said predetermined limit value is a maximum size floating point number that can be represented with said exponent value and said mantissa value. 
     
     
         15 . A method as claimed in any one of  claims 13  and  14 , wherein said step of calculating a scaling factor includes the step of identify a highest integer exponent value B of said plurality of component values. 
     
     
         16 . A method as claimed in  claim 15 , wherein said step of calculating said scaling factor sets C as equal to −B. 
     
     
         17 . A method as claimed in  claim 15 , wherein B is subject to a predetermined integer offset O and said step of calculating said scaling factor sets C as equal to a bitwise inversion of B. 
     
     
         18 . A method as claimed in any one of  claims 13  to  17 , wherein said step of scaling each of said plurality of components comprises a step of multiplying each of said plurality of components by said scaling factor, said step of multiplying identifying a case of multiplying a signed zero value given by (−1) SZ *0, where SZ is a sign value of said signed zero value, by a signed infinity value (−1) SI *∞, where SI is a sign value of said signed infinity value and generating as a corresponding component within said scaled floating point vector a predetermined value given by (−1) (SZ+SI) *PSV, where PSV is a predetermined substitute value. 
     
     
         19 . A method as claimed in  claim 18 , wherein said predetermined substitute value is 1. 
     
     
         20 . A method as claimed in  claim 18 , wherein said predetermined substitute value is 2. 
     
     
         21 . A method as claimed in  claim 13 , wherein said step of calculating a scaling value comprises the steps of:
 decoding an approximate reciprocal value generating instruction that has an input operand comprising a floating point number with an integer exponent value E and a mantissa value M; and   generating said scaling value with a scaling value exponent C that is dependent upon E and a mantissa that represents 1.   
     
     
         22 . A method as claimed in  claim 21 , wherein C is −E. 
     
     
         23 . A method as claimed in  claim 21 , wherein E is subject to a predetermined integer offset O, and C is a bitwise inversion of E. 
     
     
         24 . A method as claimed in  claim 13 , wherein said step of scaling said plurality of component values comprises the steps of:
 decoding a modified multiply instruction that has as input operands two floating point numbers; and   when one of said two floating point numbers is a signed zero value given by (−1) SZ *0, where SZ is a sign value of said signed zero value, and another of said two floating point numbers is a signed infinity value (−1) SI *∞, where SI is a sign value of said signed infinity value, generating as a scaled component value a predetermined value given by (−1) (SZ+SI) *PSV, where PSV is a predetermined substitute value.   
     
     
         25 . A method as claimed in  claim 24 , wherein said predetermined substitute value is 1. 
     
     
         26 . A method as claimed in  claim 24 , wherein said predetermined substitute value is 2. 
     
     
         27 . A method as claimed in any one of  claims 24  to  26 , wherein for other values of said two floating point numbers, said scaled component value has a value in according with a floating point product of said two floating point numbers as specified by IEEE Standard 754. 
     
     
         28 . A method as claimed in any one of  claims 24  to  28 , wherein said modified multiply instruction is a vector instruction operating upon a plurality of sets of input operands, each set of input operands being processed as specified for said two floating point numbers. 
     
     
         29 . Apparatus for normalising a vector floating point value having a plurality of components, each of said plurality of components including an integer exponent value and a mantissa value, said apparatus comprising processing circuitry configured to perform the steps of:
 calculating a scaling value in dependence upon said vector floating point value;   scaling each of said plurality of components in dependence upon said scaling value to generate a scaled vector floating point value having a plurality of scaled components;   calculating a magnitude of said scaled vector floating point value; and   dividing each of said plurality of scaled components by said magnitude to generate a normalised vector floating point value; wherein   said step of calculating a scaling value generates a scaling value of 2 C , where C is an integer value selected such that a sum of squares of said plurality of scaled components is less than a predetermined limit value.   
     
     
         30 . Apparatus for normalising a vector floating point value having a plurality of components, each of said plurality of components including an integer exponent value and a mantissa value, said apparatus comprising processing means for performing the steps of:
 calculating a scaling value in dependence upon said vector floating point value;   scaling each of said plurality of components in dependence upon said scaling value to generate a scaled vector floating point value having a plurality of scaled components;   calculating a magnitude of said scaled vector floating point value; and   dividing each of said plurality of scaled components by said magnitude to generate a normalised vector floating point value; wherein   said step of calculating a scaling value generates a scaling value of 2 C , where C is an integer value selected such that a sum of squares of said plurality of scaled components is less than a predetermined limit value.   
     
     
         31 . A virtual machine comprising a computer executing a program to provide an apparatus as claimed in any one of  claims 1  to  4 . 
     
     
         32 . A virtual machine comprising a computer executing a program to provide an apparatus as claimed in any one of  claims 6  to  11 . 
     
     
         33 . A virtual machine comprising a computer executing a program to provide an apparatus as claimed in any one of  claims 29  and  30 . 
     
     
         34 . A computer program product having a non-transitory form and storing a computer program for controlling a data processing apparatus to perform data processing in response to program instructions, wherein said computer program includes an approximate reciprocal value generating instruction for controlling said data processing apparatus to perform processing in accordance with the method of  claim 5 . 
     
     
         35 . A computer program product having a non-transitory form and storing a computer program for controlling a data processing apparatus to perform data processing in response to program instructions, wherein said computer program includes an modified multiply instruction for controlling said data processing apparatus to perform processing in accordance with the method of  claim 12 . 
     
     
         36 . Apparatus for processing data substantially as hereinbefore described with reference to the accompanying drawings. 
     
     
         37 . A method of processing data substantially as hereinbefore described with reference to the accompanying drawings. 
     
     
         38 . A virtual machine substantially as hereinbefore described with reference to the accompanying drawings. 
     
     
         39 . A computer program product substantially as hereinbefore described with reference to the accompanying drawings.