Transistor having a stressed body

Abstract

An embodiment of a transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

1 . A transistor, comprising:
 a body; and   a substrate including a semiconductor region other than a source/drain region, the semiconductor region configured to stress a portion of the body.   
     
     
         2 . The transistor of  claim 1  wherein the portion of the body includes a channel region. 
     
     
         3 . A transistor, comprising:
 a body;   a substrate; and   a source/drain region disposed outside of the substrate and configured to stress a portion of the body.   
     
     
         4 . The transistor of  claim 3  wherein the substrate includes a semiconductor region that is configured to stress the portion of the body. 
     
     
         5 . The transistor of  claim 1  wherein the semiconductor region is configured to stress the portion of the body by imparting a tensile stress to the portion of the body. 
     
     
         6 . The transistor of  claim 1  wherein the semiconductor region is configured to stress the portion of the body by imparting a compressive stress to the portion of the body. 
     
     
         7 . The transistor of  claim 1 , further comprising a stressing dopant disposed within the semiconductor region. 
     
     
         8 . The transistor of  claim 1 , further comprising carbon disposed within the semiconductor region. 
     
     
         9 . The transistor of  claim 1 , further comprising germanium disposed within the semiconductor region. 
     
     
         10 . The transistor of  claim 1 , further comprising a source/drain region configured to stress the portion of the body. 
     
     
         11 . The transistor of  claim 3 , further comprising:
 an insulator disposed over the substrate;   wherein the body is disposed over the insulator; and   wherein the source/drain region is disposed over the insulator.   
     
     
         12 . The transistor of  claim 1 , further comprising:
 an insulator;   wherein the body is disposed over the insulator; and   wherein the semiconductor region is disposed beneath the insulator.   
     
     
         13 . An integrated circuit, comprising:
 a transistor, including
 a body; and 
 a substrate having a semiconductor region other than a source/drain region, the semiconductor region configured to stress a portion of the body. 
   
     
     
         14 . The integrated circuit of  claim 13  wherein the transistor includes an N-channel field-effect transistor. 
     
     
         15 . The integrated circuit of  claim 13  wherein the transistor includes a P-channel field-effect transistor. 
     
     
         16 . A system, comprising:
 a first integrated circuit including
 a transistor, including
 a body; and 
 a substrate including a semiconductor region other than a source/drain region, the semiconductor region configured to stress a portion of the body; and 
 
   a second integrated circuit coupled to the first integrated circuit.   
     
     
         17 . The system of  claim 16  wherein one of the first and second integrated circuits includes a controller. 
     
     
         18 . The system of  claim 16  wherein the first and second integrated circuits are disposed on a same die. 
     
     
         19 . The system of  claim 16  wherein the first and second integrated circuits are disposed on respective dies. 
     
     
         20 . A method, comprising:
 forming a body; and   forming in a substrate a non-source/drain semiconductor region that imparts a stress to a portion of the body.   
     
     
         21 . The method of  claim 20  wherein forming the semiconductor region includes:
 implanting a stress-inducing dopant into the semiconductor region; and 
 annealing the semiconductor region. 
 
     
     
         22 . The method of  claim 20  wherein forming the semiconductor region includes:
 implanting a dopant into the semiconductor region using a mask; and 
 implanting another stress-inducting dopant into the semiconductor region using the same mask. 
 
     
     
         23 . The method of  claim 20  wherein:
 the semiconductor region includes a substrate; and 
 forming the semiconductor region includes,
 implanting a dopant into the substrate using a mask, 
 implanting another stress-inducting dopant into the substrate using the same mask, and 
 annealing the substrate. 
 
 
     
     
         24 . The method of  claim 20  wherein:
 the semiconductor region includes a source/drain region; and 
 forming the semiconductor region includes,
 implanting a dopant into the source/drain region using a mask, 
 implanting another stress-inducting dopant into the source/drain region using the same mask, and 
 
 annealing the source/drain region. 
 
     
     
         25 . The method of  claim 20  wherein:
 forming the body includes forming the body over an insulator; 
 the semiconductor region includes a substrate disposed under the insulator; and 
 forming the semiconductor region includes,
 implanting a dopant through the insulator and into the substrate using a mask, 
 implanting another stress-inducting dopant through the insulator and into the substrate using the same mask, and 
 
 annealing the substrate. 
 
     
     
         26 . The method of  claim 20  wherein forming the semiconductor region includes forming the semiconductor region such that the forming semiconductor region includes a stress-inducing dopant. 
     
     
         27 . The method of  claim 20  wherein forming the semiconductor region includes growing the semiconductor region such that the growing semiconductor region includes a stress-inducing dopant. 
     
     
         28 . The method of  claim 20  wherein forming the semiconductor region includes depositing the semiconductor region such that the depositing semiconductor region includes a stress-inducing dopant.