Iii-v compound semiconductor device having dopant layer and method of making the same

Abstract

A semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate;   a channel layer of at least one III-V semiconductor compound above the semiconductor substrate;   a gate electrode above a first portion of the channel layer;   a source region and a drain region above a second portion of the channel layer; and   a dopant layer comprising at least one dopant contacting the second portion of the channel layer.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the dopant layer is above the channel layer and below the source or the drain (S/D) region. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the source region and the drain region comprise a metallic ternary material. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the metallic ternary material is a nickelide of a III-V semiconductor compound. 
     
     
         5 . The semiconductor device of  claim 2 , further comprising a spacer which is disposed along a side wall of the gate electrode. 
     
     
         6 . The semiconductor device of  claim 5 , wherein a portion of the dopant layer is underneath the spacer. 
     
     
         7 . The semiconductor device of  claim 5 , wherein the source region and the drain region are recessed so that a portion of the source region and the drain region is below a bottom height of the spacer. 
     
     
         8 . The semiconductor device of  claim 2 , wherein the device is an NMOS transistor, and the channel layer is In x Ga (1-x) As, with x>0.7. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the dopant is selected from the group consisting of sulfur and silicon. 
     
     
         10 . The semiconductor device of  claim 2 , wherein the device is a PMOS transistor, and the channel layer is In y Ga (1-y) As, with 0<y<1. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the dopant is carbon. 
     
     
         12 . A method for forming a semiconductor device which comprises:
 providing a channel layer of at least one III-V semiconductor compound above a semiconductor substrate;   forming a gate electrode above a first portion of the channel layer;   providing a dopant layer comprising at least one dopant contacting the channel layer; and   forming a source region and a drain region above a second portion of the channel layer.   
     
     
         13 . The method of  claim 12 , wherein the step of providing the dopant layer includes forming the dopant layer above the channel layer and below the source or the drain (S/D) region. 
     
     
         14 . The method of  claim 13 , wherein the dopant is formed through a process selected from the group consisting of a monolayer doping process, an in-situ doping process and an implantation process. 
     
     
         15 . The method of  claim 13 , further comprising forming a metallic ternary material with a III-V semiconductor compound in the source region and the drain region. 
     
     
         16 . The method of  claim 15 , wherein the step of forming a metallic ternary material comprises a step of depositing a metal layer on the III-V semiconductor compound in the source region and the drain region, followed by a step of annealing at a raised temperature. 
     
     
         17 . The method of  claim 13 , further comprising disposing a spacer along a side wall of the gate electrode. 
     
     
         18 . The method of  claim 17 , further comprising a step of recessing the channel layer before providing the dopant layer comprising at least one dopant contacting the channel layer. 
     
     
         19 . The method of  claim 18 , wherein the step of forming the source region and the drain region above the second portion of the channel layer comprises disposing a portion of the source region and the drain region below a bottom height of the spacer. 
     
     
         20 . A method for forming a NMOS semiconductor device which comprises:
 providing a channel layer of at least one III-V semiconductor compound above a semiconductor substrate;   forming a gate electrode above a first portion of the channel layer;   forming a source region and a drain region above a second portion of the channel layer;   providing a dopant layer comprising at least one dopant contacting the channel layer by doping the source and the drain region through a process of monolayer doping or ion implantation; and   forming a metallic ternary material with a III-V semiconductor compound in the source region and the drain region,   wherein the step of forming a metallic ternary material comprises a step of depositing a metal layer on the III-V semiconductor compound in the source region and the drain region, followed by a step of annealing at a raised temperature.