Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory

Abstract

A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate.

We claim: 
     
         1 . A method for performing an erase iteration of an erase operation for a set of non-volatile storage elements which is formed on a substrate, the set of non-volatile storage elements comprises a string of series-connected non-volatile storage elements between first and second select transistors, the series-connected non-volatile storage elements comprise a first non-user data non-volatile storage element adjacent to the first select transistor, the method comprising:
 increasing an erase voltage of the substrate to provide a first source of capacitive coupling up to a control gate of the first select gate transistor, while floating a voltage of the control gate of the first select gate transistor, but not floating a voltage of a control gate of the first non-user data non-volatile storage element; and   increasing the erase voltage of the substrate to provide a second source of capacitive coupling up to the control gate of first select gate transistor and to the control gate of the first non-user data non-volatile storage element, while floating the voltage of the control gate of the first select gate transistor and the voltage of the control gate of the first non-user data non-volatile storage element.   
     
     
         2 . The method of  claim 1 , wherein:
 the series-connected non-volatile storage elements comprise a second non-user data non-volatile storage element adjacent to the second select transistor;   the first source of capacitive coupling up is provided to a control gate of the second select gate transistor, while floating a voltage of the control gate of the second select gate transistor; and   the second source of capacitive coupling up is provided to the control gate of second select gate transistor and to the control gate of the second non-user data non-volatile storage element, while floating the voltage of the control gate of the second select gate transistor and the voltage of the second non-user data non-volatile storage element.   
     
     
         3 . The method of  claim 1 , wherein:
 the increasing of the erase voltage to provide the first source of capacitive coupling occurs before the increasing of the erase voltage to provide the second source of capacitive coupling.   
     
     
         4 . The method of  claim 1 , wherein:
 the series-connected non-volatile storage elements comprise a second non-user data non-volatile storage element adjacent to the first non-user data non-volatile storage element; and   a voltage of a control gate of the second non-user data non-volatile storage element is fixed at a first level during the increasing of the erase voltage to provide the first source of capacitive coupling and the increasing of the erase voltage to provide the second source of capacitive coupling.   
     
     
         5 . The method of  claim 4 , wherein:
 the series-connected non-volatile storage elements comprise a non-volatile storage element which is designated to store user data and which is adjacent to the second non-user data non-volatile storage element; and   a voltage of a control gate of the non-volatile storage element which is designated to store user data is fixed at second level, lower than or equal to the first level, during the increasing of the erase voltage to provide the first source of capacitive coupling and the increasing of the erase voltage to provide the second source of capacitive coupling.   
     
     
         6 . The method of  claim 1 , further comprising:
 fixing the erase voltage of the substrate at a non-zero level before the increasing the erase voltage of the substrate to provide the first source of capacitive coupling; and   driving the control gate of first select gate transistor and the control gate of the first non-user data non-volatile storage element during the fixing of the erase voltage of the substrate.   
     
     
         7 . The method of  claim 1 , further comprising:
 fixing the erase voltage of the substrate after the increasing of the erase voltage to provide the first source of capacitive coupling and before the increasing of the erase voltage to provide the second source of capacitive coupling, and while floating the voltage of the control gate of the first select gate transistor.   
     
     
         8 . The method of  claim 1 , wherein:
 the series-connected non-volatile storage elements comprise a second non-user data non-volatile storage element adjacent to the first non-user data non-volatile storage element; and   the method further comprises increasing the erase voltage of the substrate to provide a third source of capacitive coupling up to a control gate of the second non-user data non-volatile storage element, while floating the voltage of the control gate of the first select gate transistor and the voltage of the control gate of the first and the second non-user data non-volatile storage element, the third source of capacitive coupling is provided after the second source of capacitive coupling, the increasing the erase voltage of the substrate to provide the first source of capacitive coupling occurs before the increasing the erase voltage of the substrate to provide the second source of capacitive coupling, and the increasing the erase voltage of the substrate to provide the second source of capacitive coupling occurs before the increasing the erase voltage of the substrate to provide the third source of capacitive coupling.   
     
     
         9 . The method of  claim 1 , wherein:
 the increasing of the erase voltage to provide the first and second sources of capacitive coupling comprises providing a continuous increasing of the erase voltage of the substrate.   
     
     
         10 . The method of  claim 9 , further comprising:
 fixing the erase voltage of the substrate at a non-zero level before the continuous increasing of the erase voltage of the substrate; and   driving the control gate of first select gate transistor and the control gate of the first non-user data non-volatile storage element during the fixing of the erase voltage of the substrate.   
     
     
         11 . The method of  claim 9 , wherein:
 the floating the voltage of the control gate of the first select gate transistor during the increasing the erase voltage of the substrate to provide the first source of capacitive coupling, is initiated at one specified time after initiating the continuous increasing of the erase voltage of the substrate;   the floating the voltage of the control gate of the first non-user data non-volatile storage element during the increasing the erase voltage of the substrate to provide the second source of capacitive coupling is initiated at another specified time after the initiating the continuous increasing of the erase voltage of the substrate; the another specified time is after the one specified time.   
     
     
         12 . The method of  claim 1 , wherein:
 the increasing the erase voltage of the substrate to provide the first source of capacitive coupling occurs before the increasing the erase voltage of the substrate to provide the second source of capacitive coupling; and   the increasing the erase voltage of the substrate to provide the first source of capacitive coupling, and the increasing the erase voltage of the substrate to provide the second source of capacitive coupling, occur in an erase iteration of an erase-verify iteration; and   the method further comprises performing a verify iteration of the erase-verify iteration after performing the erase iteration.   
     
     
         13 . The method of  claim 12 , wherein:
 the voltage of the control gate of the first select gate transistor is capacitively coupled to a respective peak level in the erase iteration by the increasing the erase voltage of the substrate to provide the first source of capacitive coupling and the increasing the erase voltage of the substrate to provide the second source of capacitive coupling; and   the voltage of the control gate of the first non-user data non-volatile storage element is capacitively coupled to a respective peak level in the erase iteration by the increasing the erase voltage of the substrate to provide the second source of capacitive coupling.   
     
     
         14 . The method of  claim 12 , wherein:
 the increasing the erase voltage of the substrate to provide the second source of capacitive coupling comprises increasing the erase voltage to a respective peak level in the erase iteration.   
     
     
         15 . A non-volatile storage system, comprising:
 a set of non-volatile storage elements which is formed on a substrate, the set of non-volatile storage elements comprises a string of series-connected non-volatile storage elements between first and second select gate transistors, the series-connected non-volatile storage elements comprise a first non-volatile storage element adjacent to the first select gate transistor, the first non-volatile storage element comprises a control gate and the first select gate transistor comprises a control gate; and   a control circuit, the control circuit, to perform an erase iteration of an erase operation for the set of non-volatile storage elements: throughout one time period, provides capacitive coupling from the substrate to the control gate of the first select gate transistor and prevents capacitive coupling from the substrate to the control gate of the first non-volatile storage element, and throughout another time period, non-overlapping with the one time period, provides capacitive coupling from the substrate to the control gate of the first select gate transistor and to the control gate of the first non-volatile storage element.   
     
     
         16 . The non-volatile storage system of  claim 15 , wherein:
 the control circuit, throughout the one time period, increases a voltage of the substrate, floats a voltage of the control gate of the first select gate transistor and drives a voltage of the first non-volatile storage element, and throughout the another time period, increases the voltage of the substrate, floats the voltage of the control gate of the first select gate transistor and floats the voltage of the first non-volatile storage element.   
     
     
         17 . The non-volatile storage system of  claim 16 , wherein:
 the increase of the voltage of the substrate is continuous throughout a time period which comprises the one time period and the another time period.   
     
     
         18 . The non-volatile storage system of  claim 16 , wherein:
 the increase of the voltage in the one time period comprises a voltage ramp, and the increase of the voltage in the another time period comprises another voltage ramp.   
     
     
         19 . A method for performing an erase iteration of an erase operation for a NAND string of non-volatile storage elements which is formed on a substrate, the NAND string comprises a string of series-connected non-volatile storage elements between first and second select transistors, the series-connected non-volatile storage elements comprise a first non-volatile storage element adjacent to the first select transistor, the method comprising:
 increasing an erase voltage of the substrate while floating a voltage of a control gate of the first select gate transistor, and while driving a voltage of the control gate of the first non-volatile storage element; and   further increasing the erase voltage of the substrate while floating the voltage of the control gate of the first select gate transistor and the voltage of the control gate of the first non-volatile storage element.   
     
     
         20 . The method of  claim 19 , wherein:
 the erase voltage of the substrate is increased in multiple steps as an increasing staircase waveform.   
     
     
         21 . The method of  claim 19 , wherein:
 the erase voltage of the substrate is increased as a continuous ramp.