US2013316501A1PendingUtilityA1

Ultra-thin near-hermetic package based on rainier

51
Assignee: TESSERA INCPriority: May 11, 2007Filed: Jul 31, 2013Published: Nov 28, 2013
Est. expiryMay 11, 2027(~0.8 yrs left)· nominal 20-yr term from priority
H10W 90/701H10W 70/65H10W 76/153H10W 74/01H10W 20/01Y10T29/49165H01L 21/768H01L 21/56
51
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.

Claims

exact text as granted — not AI-modified
1 . A method of making a microelectronic package comprising the steps of:
 (a) providing a dielectric layer having top and bottom surfaces, terminals exposed at the bottom surface, and a wall projecting upwardly from the top surface;   (b) mounting a microelectronic element over a region of the top surface surrounded by the wall and electrically connecting the microelectronic element to at least some of the terminals; and   (c) bonding a lid to the wall so that the lid extends over the microelectronic element and the microelectronic element.   
     
     
         2 . The method of making a microelectronic package according to  claim 1 , wherein the bonding step includes metallurgically bonding the metallic lid to the wall. 
     
     
         3 . The method of making a microelectronic package according to  claim 1 , further comprising:
 filling a mold compound into the region after said mounting by using the wall as a dam for the mold compound being in a liquid state.   
     
     
         4 . A method of making a microelectronic chip carrier, comprising the steps of:
 (a) providing a composite metallic plate including a base layer of a metal and a conductive layer;   (b) etching the base layer to form a wall;   (c) etching the conductive layer to separate the conductive layer into individual conductive elements; and   (d) uniting the conductive elements and wall with a dielectric layer so that the wall projects upwardly away from the dielectric layer and encircle a region of the dielectric layer, and so that the conductive elements are carried on the region of the dielectric layer.   
     
     
         5 . The method as claimed in  claim 4  wherein the step of uniting the conductive elements and the wall with the dielectric layer includes uniting the dielectric layer with the composite metallic plate after etching the conductive layer to separate the conductive layer into individual conductive elements, and before etching the base layer to form the wall. 
     
     
         6 . The method as claimed in  claim 4  wherein the step of uniting the conductive elements and the wall with the dielectric layer is performed by uniting the dielectric layer with the composite metallic plate before etching the base layer to form the wall, and wherein the step of etching the conductive layer is performed during or after etching the base layer to form the wall. 
     
     
         7 . The method as claimed in  claim 6  wherein the step of providing the composite metallic plate includes providing islands of an etch-resistant material between the base layer and the conductive layer in a pattern corresponding to the conductive elements to be formed, and wherein the step of etching the conductive layer includes exposing a the conductive layer to an etchant so that the islands of etch-resistant material protect portions of the conductive layer from the etchant and portions of the conductive layer between the islands are removed. 
     
     
         8 . The method as claimed in  claim 4  wherein the conductive elements include terminals, the method further comprising forming holes in the dielectric layer so that the terminals are exposed at a bottom surface of the dielectric layer facing away from the wall.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.