Programming of gated phase-change memory cells

Abstract

A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧2 programmable cell-states including an amorphous RESET state and at least one crystalline state includes applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance.

1 . An apparatus for programming gated phase-change memory cells, each with a gate, source and drain, having s≧2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the apparatus comprising:
 a signal generator configured to apply a programming signal between the source and drain of a memory cell to program the cell to a desired cell-state; 
 a bias voltage generator configured to apply a bias voltage to the gate of a cell; and 
 a controller configured to control the signal generator and bias voltage generator such that, when programming a cell from a crystalline state to the RESET state, the bias voltage generator applies a bias voltage to the gate of the cell to increase the cell resistance. 
 
     
     
         2 . The apparatus of  claim 1 , wherein the bias voltage level is set to increase the cell resistance to a value at or near a predetermined maximum value for the crystalline state. 
     
     
         3 . The apparatus of  claim 1 , wherein the Fermi level for a cell in a crystalline state is in or near the conduction band, and wherein the bias voltage polarity is set to move the Fermi level towards the valence band on applying the bias voltage. 
     
     
         4 . The apparatus of  claim 1 , wherein the Fermi level for a cell in a crystalline state is in or near the valence band, and wherein the bias voltage polarity is set to move the Fermi level towards the conduction band on applying the bias voltage. 
     
     
         5 . The apparatus of  claim 1 , wherein the controller is adapted to control the signal generator and bias voltage generator such that, when programming a cell to a crystalline state, zero bias voltage is applied to the gate of the cell. 
     
     
         6 . The apparatus of  claim 1 , wherein the controller is adapted to control the signal generator and bias voltage generator such that, when programming a cell to a crystalline state, a bias voltage for that state is applied to the gate of the cell to program that crystalline state on application of the programming signal. 
     
     
         7 . The apparatus of  claim 1 , wherein each memory cell is connected to a respective access device for controlling access to that cell for programming, and wherein the signal generator is adapted to control access to a memory cell via the access device when applying a programming signal to program the cell. 
     
     
         8 . The apparatus of  claim 2 , wherein s=2. 
     
     
         9 . The apparatus of  claim 2 , wherein s>2.