Epitaxially Thickened Doped or Undoped Core Nanowire FET Structure and Method for Increasing Effective Device Width

Abstract

Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX. Nanowire cores and pads are etched in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial shells are formed surrounding each of the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores/epitaxial shells, wherein the portions of the nanowire cores/epitaxial shells surrounded by the gate stack serve as channels of the device, and wherein the pads and portions of the nanowire cores/epitaxial shells that extend out from the gate stack serve as source and drain regions of the device.

What is claimed is: 
     
         1 . A method of fabricating a field effect transistor (FET) device, comprising the steps of:
 providing a semiconductor-on-insulator (SOI) wafer having an SOI layer over a buried oxide (BOX);   etching nanowire cores and pads in the SOI layer, wherein the pads are attached at opposite ends of the nanowire cores in a ladder-like configuration;   suspending the nanowire cores over the BOX;   forming epitaxial shells surrounding each of the nanowire cores; and   forming a gate stack that surrounds at least a portion of each of the nanowire cores and the epitaxial shells, wherein the portions of the nanowire cores and the epitaxial shells surrounded by the gate stack serve as channels of the device, wherein the pads and portions of the nanowire cores and the epitaxial shells that extend out from the gate stack serve as source and drain regions of the device, and wherein the channels of the device have a pitch of from about 5 nm to about 50 nm.   
     
     
         2 . The method of  claim 1 , wherein the channels of the device have a pitch of from about 20 nm to about 40 nm. 
     
     
         3 . The method of  claim 1 , further comprising the step of:
 thinning the nanowire cores.   
     
     
         4 . The method of  claim 1 , wherein the SOI layer comprises a semiconducting material selected from the group consisting of: silicon, silicon germanium and silicon carbon. 
     
     
         5 . The method of  claim 1 , wherein the nanowire cores are doped with either an n-type dopant or a p-type dopant. 
     
     
         6 . The method of  claim 1 , wherein the nanowire cores are undoped. 
     
     
         7 . The method of  claim 1 , wherein the step of thinning the nanowire cores comprises the steps of:
 oxidizing the nanowires to form an oxide on the nanowire cores;   etching the oxide formed on the nanowire cores; and   repeating the oxidizing and etching steps until a desired nanowire dimension is achieved.   
     
     
         8 . The method of  claim 1 , wherein the epitaxial shells are doped with either an n-type dopant or a p-type dopant. 
     
     
         9 . The method of  claim 1 , wherein the epitaxial shells are undoped. 
     
     
         10 . The method of  claim 1 , wherein the epitaxial shells comprise epitaxial silicon, silicon germanium or silicon carbon. 
     
     
         11 . The method of  claim 1 , wherein during the step of forming the epitaxial shells surrounding each of the nanowire cores, an epitaxial material is formed on the pads, the method further comprising the step of:
 forming a contact material on the epitaxial material and on the portions of the epitaxial shells that extend out from the gate stack.   
     
     
         12 . The method of  claim 11 , wherein the contact material comprises a silicide. 
     
     
         13 . The method of  claim 1 , further comprising the step of:
 forming spacers on opposite sides of the gate stack.   
     
     
         14 . The method of  claim 1 , further comprising the step of:
 annealing the nanowire cores under conditions sufficient to smoothen the nanowires.   
     
     
         15 . The method of  claim 14 , wherein the conditions comprise a temperature of from about 600° C. to about 1,000° C. in an atmosphere containing hydrogen. 
     
     
         16 . The method of  claim 1 , wherein the step of forming the gate stack comprises the steps of:
 depositing a conformal gate dielectric film around the nanowire cores and the epitaxial shells;   depositing a conformal metal gate film over the conformal gate dielectric film;   depositing polysilicon over the conformal metal gate film; and   patterning the polysilicon, the conformal gate dielectric film and the conformal metal gate film using a hardmask to form the gate stack.   
     
     
         17 . The method of  claim 16 , wherein the conformal gate dielectric film is selected from the group consisting of: silicon dioxide, silicon oxynitride, hafnium oxide and hafnium silicate. 
     
     
         18 . The method of  claim 16 , wherein the conformal metal gate film is selected from the group consisting of: tantalum nitride and titanium nitride. 
     
     
         19 . A FET device, comprising:
 a wafer having a BOX;   nanowire cores and pads attached at opposite ends of the nanowire cores in a ladder-like configuration on the BOX, wherein the nanowire cores are suspended over the BOX;   epitaxial shells surrounding each of the nanowire cores; and   a gate stack that surrounds at least a portion of each of the nanowire cores and the epitaxial shells, wherein the portions of the nanowire cores and the epitaxial shells surrounded by the gate stack serve as channels of the device, wherein the pads and portions of the nanowire cores and the epitaxial shells that extend out from the gate stack serve as source and drain regions of the device, and wherein the channels of the device have a pitch of from about 5 nm to about 50 nm.   
     
     
         20 . The FET device of  claim 19 , wherein the nanowire cores are doped with either an n-type dopant or a p-type dopant. 
     
     
         21 . The FET device of  claim 19 , wherein the nanowire cores are undoped. 
     
     
         22 . The FET device of  claim 19 , wherein the epitaxial shells are doped with either an n-type dopant or a p-type dopant. 
     
     
         23 . The FET device of  claim 19 , wherein the epitaxial shells are undoped. 
     
     
         24 . The FET device of  claim 19 , wherein the channels of the device have a pitch of from about 20 nm to about 40 nm.