Structure And Method To Realize Conformal Doping In Deep Trench Applications

Abstract

The specification and drawings present a new method, ASIC and computer/software related product (e.g., a computer readable memory) are presented for realizing conformal doping in embedded deep trench applications in the ASIC. A common SOI substrate with intrinsic or low dopant concentration is used for manufacturing such ASICs comprising a logic area having MOSFETs utilizing, for example, ultra thin body and box technology and an eDRAM area having deep trench capacitors with the conformal doping.

1 - 20 . (canceled) 
     
     
         21 . An integrated circuit comprising a logic area and an embedded dynamic random access memory (eDRAM) area, comprising:
 a semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer, at least the first semiconducting layer is intrinsic or comprising a dopant of low concentration;   a plurality of capacitors in the DRAM area formed using deep trenches in the SOI substrate, wherein regions adjacent to sidewalls and bottoms in the first semiconductor layer of the SOI substrate comprise a further dopant of high concentration around the deep trenches provided at least by a thermal infusion.   
     
     
         22 . The integrated circuit of  claim 21 , wherein the SOI substrate comprises at least a pad oxide layer and a pad nitride layer on the top of the second semiconductor layer. 
     
     
         23 . The integrated circuit of  claim 21 , wherein the first or second semiconductor layer in the SOI is made of at least one of Si, Ge, GaP, InAs, InP and SiGe. 
     
     
         24 . The integrated circuit of  claim 21 , wherein the first an second semiconductor layers in the SOI are made of a same material. 
     
     
         25 . The integrated circuit of  claim 21 , wherein the logic area comprises a plurality of MOSFET transistors fabricated using an ultrathin body and box technology. 
     
     
         26 . The integrated circuit of  claim 25 , wherein the MOSFET transistors are n-type and p-type. 
     
     
         27 . The integrated circuit of  claim 21 , wherein the first and second semiconductor layers comprise the low concentration dopant of n-type. 
     
     
         28 . The integrated circuit of  claim 21 , wherein the first and second semiconductor layers comprise the low concentration dopant of p-type. 
     
     
         29 . The integrated circuit of  claim 21 , wherein the further dopant is n-type. 
     
     
         30 . The integrated circuit of  claim 21 , wherein the further dopant is p-type. 
     
     
         31 . The integrated circuit of  claim 21 , wherein the further dopant of high concentration has a concentration of 10 19 -10 21  atoms/cm 3  or more. 
     
     
         32 . The integrated circuit of  claim 21 , wherein the dopant of low concentration and the further dopant of high concentration are n-type dopants. 
     
     
         33 . The integrated circuit of  claim 21 , wherein the dopant of low concentration and the further dopant of high concentration are p-type dopants. 
     
     
         34 . The integrated circuit of clai  21 , therein the dopant of low concentration has a concentration 10 13 -10 16  atoms/cm 3 . 
     
     
         35 . The integrated circuit of  claim 21 , wherein the first and second semiconducting layers are intrinsic or comprising the dopant of low concentration. 
     
     
         36 . The integrated circuit of  claim 21 , wherein regions adjacent to sidewalls and bottoms in the first semiconductor layer of the SOI substrate comprise an additional further dopant of a same type as the further dopant implanted using an angled ion implantation into the semiconductor epitaxial film on the sidewalls and bottoms of the deep trenches in the SOI. 
     
     
         37 . The integrated circuit of  claim 36 , wherein the additional further dopant is a different material than the further dopant. 
     
     
         38 . The integrated circuit of  claim 36 , wherein the further dopant of high concentration alone or combined with an additional further dopant has a concentration of 10 19 -10 21  atoms/cm 3  or more.