Apparatus and Method for Multiple Gate Transistors

Abstract

An apparatus comprises a substrate having a first crystal orientation and an active region, wherein an upper portion of the active region is of a second crystal orientation and the upper portion of the active region is wrapped by a gate structure around two sides. The apparatus further comprises a trench surrounded by isolation regions, wherein the upper portion of the active region is over top surfaces of the isolation regions.

What is claimed is: 
     
         1 . An apparatus comprising:
 a substrate having a first crystal orientation;   an active region formed over the substrate, wherein:
 an upper portion of the active region is of a second crystal orientation; and 
 the upper portion of the active region is wrapped by a gate structure around two sides; and 
   a trench formed in the substrate and surrounded by isolation regions, wherein:
 the upper portion of the active region is over top surfaces of the isolation regions. 
   
     
     
         2 . The apparatus of  claim 1 , wherein:
 the substrate is of a <001> crystal orientation; and   the upper portion of the active region is of a <111> crystal orientation.   
     
     
         3 . The apparatus of  claim 1 , wherein:
 the substrate is formed of silicon; and   the active region is formed of germanium.   
     
     
         4 . The apparatus of  claim 1 , wherein the active region comprises:
 a first portion formed of a first semiconductor material;   a second portion formed of a second semiconductor material, wherein the second portion is formed over the first portion; and   a third portion formed of a third semiconductor material, wherein the third portion is formed over the second portion.   
     
     
         5 . The apparatus of  claim 4 , wherein:
 the first semiconductor material, the second semiconductor material and the third semiconductor materials are selected from the group consisting of group IV, group III-V and group II-VI semiconductor materials.   
     
     
         6 . The apparatus of  claim 1 , wherein the upper portion of the active region is triangular in shape from a cross sectional view. 
     
     
         7 . The apparatus of  claim 1 , further comprising:
 a gate dielectric layer formed between the gate structure and the upper portion of the active region.   
     
     
         8 . A device comprising:
 a substrate having a <001> crystal orientation, wherein the substrate is formed of a first semiconductor material;   a plurality of isolation regions formed over the substrate, wherein two adjacent isolation regions form a trench in the substrate;   a channel region formed over the substrate and connected between a first drain/source region and a second drain/source region, wherein:
 the channel region is formed of a second semiconductor material; 
 the channel region is triangular in shape from a cross sectional view; and 
 the channel region is of a <111> crystal orientation; and 
   a gate electrode wrapping the channel region around two sides.   
     
     
         9 . The device of  claim 8 , wherein:
 the channel region is over top surfaces of the isolation region.   
     
     
         10 . The device of  claim 8 , wherein:
 a lattice constant of the second semiconductor material is of greater than a lattice constant of the first semiconductor material.   
     
     
         11 . The device of  claim 8 , further comprising:
 a semiconductor region formed in the trench, wherein the semiconductor region is coupled between the substrate and the channel region.   
     
     
         12 . The device of  claim 11 , wherein the semiconductor region comprises:
 a first layer formed of a third semiconductor material; and   a second layer formed of a fourth semiconductor material, wherein the second layer is formed over the first semiconductor.   
     
     
         13 . The device of  claim 12 , wherein:
 the third semiconductor material and the fourth semiconductor materials are selected from the group consisting of group IV, group III-V and group II-VI semiconductor materials.   
     
     
         14 . A method comprising:
 providing a substrate having a first crystal orientation, wherein the substrate is formed of a first semiconductor material;   etching away a portion of the substrate to form a trench between two adjacent isolation regions;   growing a semiconductor region in the trench over the substrate through an epitaxial growth process, wherein an upper portion of the semiconductor region is triangular in shape from a cross section view and has a second crystal orientation; and   forming a gate structure on at least two sides of the semiconductor region.   
     
     
         15 . The method of  claim 14 , further comprising:
 over-growing the semiconductor region so that the upper portion of the semiconductor region is above top surfaces of the isolation regions.   
     
     
         16 . The method of  claim 14 , further comprising:
 etching away upper portions of the isolation regions so that the upper portion of the semiconductor region is above top surfaces of the isolation regions.   
     
     
         17 . The method of  claim 14 , further comprising:
 growing a first semiconductor layer of a second semiconductor material over the substrate;   growing a second semiconductor layer of a third semiconductor material over the first semiconductor layer; and   growing a third semiconductor layer of a fourth semiconductor material over the second semiconductor layer.   
     
     
         18 . The method of  claim 14 , further comprising:
 depositing a gate dielectric layer over the semiconductor region.   
     
     
         19 . The method of  claim 14 , wherein:
 a lattice constant of the semiconductor region is greater than a lattice constant of the substrate.   
     
     
         20 . The method of  claim 14 , wherein:
 the first crystal orientation is <001>; and   the second crystal orientation is <111>.