Silicon germanium channel with silicon buffer regions for fin field effect transistor device

Abstract

A fin field effect transistor (finFET) device includes a substrate; first and second source/drain regions located on the substrate; and a fin located on the substrate between the first and second source/drain regions. The fin includes a silicon germanium channel region and first and second silicon buffer regions located in the fin adjacent to and on either side of the silicon germanium channel region. The first silicon buffer region is located between the first source/drain region and the silicon germanium channel region and the second silicon buffer region is located between the second source/drain region and the silicon germanium channel region.

1 . A fin field effect transistor (finFET) device, comprising:
 a substrate;   first and second source/drain regions located on the substrate; and   a fin located on the substrate between the first and second source/drain regions, wherein the fin comprises:
 a silicon germanium channel region; and 
 first and second silicon buffer regions located in the fin adjacent to and on either side of the silicon germanium channel region, wherein the first silicon buffer region is located between the first source/drain region and the silicon germanium channel region, and wherein the second silicon buffer region is located between the second source/drain region and the silicon germanium channel region. 
   
     
     
         2 . The finFET device of  claim 1 , further comprising inner spacers located adjacent to the first and second silicon buffer regions. 
     
     
         3 . The finFET device of  claim 2 , wherein the inner spacers comprise nitride. 
     
     
         4 . The finFET device of  claim 2 , further comprising a gate located on top of the fin, wherein the gate is located in between the inner spacers. 
     
     
         5 . The finFET device of  claim 2 , wherein the substrate comprises a silicon-on-insulator substrate comprising a top silicon layer on top of a buried oxide (BOX) layer, wherein the fin is located in a first portion of the top silicon layer on top of the BOX layer, and wherein the first and second source/drain regions are located in a second portion of the top silicon layer on top of the BOX layer. 
     
     
         6 . The finFET device of  claim 5 , wherein the inner spacers are located on the BOX layer on either side of the first and second silicon buffer regions, and adjacent to the first and second source/drain regions.