Ion implantation device and a method of semiconductor manufacturing by the implantation of boron hydride cluster ions

Abstract

A method of manufacturing a semiconductor device includes the steps of: providing a supply of molecules containing a plurality of dopant atoms into an ionization chamber, ionizing said molecules into dopant cluster ions, extracting and accelerating the dopant cluster ions with an electric field, selecting the desired cluster ions by mass analysis, modifying the final implant energy of the cluster ion through post-analysis ion optics, and implanting the dopant cluster ions into a semiconductor substrate. In general, dopant molecules contain n dopant atoms, where n is an integer number greater than 10. This method enables increasing the dopant dose rate to n times the implantation current with an equivalent per dopant atom energy of 1/n times the cluster implantation energy, while reducing the charge per dopant atom by the factor n.

What is claimed and desired to be covered by a Letters Patent is as follows: 
     
         1 - 39 . (canceled) 
     
     
         40 . A vapor source for an ion source, the vapor source comprising:
 a vaporizer defining a volume for receiving a solid feed material;   a vaporizer conduit in fluid communication with said vaporizer;   a shut off valve coupled to said vaporizer conduit;   a source block formed with a vapor conduit which forms a vapor feed for an ionization chamber;   at least one heating element for heating said vaporizer conduit, said shut-off valve and said vapor conduit   a temperature system for controlling the temperature of said vaporizer, said shut-off valve and said source block by controlling said at least one heating element.   
     
     
         41 . The vapor source as recited in  claim 40 , wherein said temperature system is a closed loop system. 
     
     
         42 . The vapor source as recited in  claim 40 , wherein said temperature control system is configured to control said vaporizer, said shut-off valve and said source block separately. 
     
     
         43 . The vapor source as recited in  claim 40 , wherein said at least one heating element includes an embedded resistive heater. 
     
     
         44 . The vapor source as recited in  claim 40 , wherein said at least one heating element includes a resistive cartridge heater. 
     
     
         45 . The vapor source as recited in  claim 40 , wherein said at least one heating element includes a silicone strip heater. 
     
     
         46 . The vapor source as recited in  claim 40 , wherein said temperature control system includes one thermocouple. 
     
     
         47 . The vapor source as recited in  claim 40 , wherein said temperature control system includes three thermocouples embedded into said vaporizer, said shut-off valve and said source block. 
     
     
         48 . The vapor source as recited in  claim 40 , wherein said temperature system includes at least one electronic temperature controller. 
     
     
         49 . The vapor source as recited in  claim 40 , wherein said temperature system includes three electronic temperature controllers for controlling the temperature of said vaporizer, said shut-off valve and said source block. 
     
     
         50 . The vapor source as recited in  claim 49 , wherein the temperature set points of said three electronic temperature controllers are user-programmable. 
     
     
         51 . A method for forming a complementary metal oxide semiconductor (CMOS) device having a substrate defining a first region and a second region, the method comprising the steps of:
 (a) isolating said first region and said second region on said substrate;   (b) forming a P-type metal oxide semiconductor (PMOS) device in one of said first or second regions, said PMOS device including a gate stack and drain extensions and drain and source regions adjacent said gate stack, said drain extensions and said drain and source regions formed with P-type cluster ions;   (c) shielding said PMOS device;   (d) forming an N-type metal oxide semiconductor (NMOS) device in the other of said first or second regions, said NMOS device including a gate stack and drain extensions and drain and source regions adjacent said gate stack, said drain extensions and said drain and source regions formed with N-type cluster ions;   (e) removing said shielding.   
     
     
         52 . The method as recited in  claim 51 , wherein step (d) includes forming drain extensions for said NMOS device with As cluster ions. 
     
     
         53 . The method as recited in  claim 51 , wherein step (d) includes forming source and drain regions for said NMOS device with As cluster ions. 
     
     
         54 . The method as recited in  claim 52 , wherein step (d) includes forming said drain extensions and said drain and source regions with As 4 H x   +  cluster ions. 
     
     
         55 . The method as recited in  claim 51 , wherein step (b) includes forming drain extensions for said PMOS device with Boron cluster ions. 
     
     
         56 . The method as recited in  claim 51 , wherein step (b) includes forming source and drain regions for said PMOS device with Boron cluster ions. 
     
     
         57 . The method as recited in  claim 55 , wherein step (b) includes forming said drain extensions and said drain and source regions with B 18 H x   +  cluster ions. 
     
     
         58 . The method as recited in  claim 51 , further including the step of:
 (f) annealing said semiconductor device.   
     
     
         59 . A complementary metal oxide semiconductor (CMOS) device comprising:
 a substrate defining a first region and a second region;   an N-type metal oxide semiconductor (NMOS) device formed on one of said first and second regions of said substrate; and   a P-type metal oxide semiconductor (PMOS) device formed on the other of said first and second regions of said substrate, wherein said NMOS and said PMOS devices are formed in part with cluster ions.   
     
     
         60 . The CMOS device as recited in  claim 59 , wherein said NMOS device includes As cluster ions. 
     
     
         61 . The CMOS device as recited in  claim 59 , wherein said As cluster ions include As 4 H x   + . 
     
     
         62 . The CMOS device as recited in  claim 59 , wherein said PMOS device includes Boron cluster ions. 
     
     
         63 . CMOS device as recited in  claim 59 , wherein said Boron cluster ions include B 18 H x   + . 
     
     
         64 . A method for forming a metal oxide semiconductor (MOS) device having a substrate defining a first region and a second region, the method comprising the steps of:
 (a) forming a well and opposing trench isolations in said first region of said substrate;   (b) forming a gate stack on said substrate between said opposing trench isolations defining exposed portions of said substrate;   (c) depositing a pad oxide onto said exposed portions of said substrate and on top of said gate stack;   (d) implanting B 18 H x   +  (where, 0≦x≦22) ions to form drain extensions between said gate stack and said opposing trench isolations;   (e) forming spacers adjacent said gate stack;   (f) implanting P-type cluster ions to form source and drain regions;   (g) providing heat treatment to activate material implanted by said doping step, thereby forming a P-type metal oxide semiconductor (MOS) device (PMOS).   
     
     
         65 . The method as recited in  claim 69 , further including the steps of:
 (a) isolating first and second regions on said substrate;   (b) forming said PMOS device in said first region; and   (c) forming an NMOS device in said second region.   
     
     
         66 . The method as recited in  claim 65 , wherein step (c) includes implanting N-type cluster ions in said second region. 
     
     
         67 . The method as recited in  claim 66 , wherein said N-type cluster ions are As 4 H x +, where 0≦x≦6. 
     
     
         68 . The method as recited in  claim 64 , wherein step (b) comprises the steps:
 i) depositing or growing a gate dielectric;   ii) depositing a polysilicon gate electrode, and   iii) patterning to form the gate stack.   
     
     
         69 . The ion source for generating boron hydride cluster ions, the ion source comprising:
 an ionization chamber in fluid communication with said source of gas, said ionization chamber formed with an electron entrance aperture for receiving an electron beam, an ion extraction aperture for enabling an ionized beam to be extracted from said ionization chamber and a vapor inlet aperture for enabling vapor to be received in said ionization chamber, said ionization chamber configured to enable ionization of said vapor by electron bombardment to create an ion beam:   a first source for generating an electron beam, said electron source disposed outside of said ionization chamber; and   a source of boron hydride vapor coupled to said vapor inlet aperture.   
     
     
         70 . The ion source as recited in  claim 69 , wherein said ion beam is a cluster ion beam. 
     
     
         71 . The ion source as recited in  claim 70 , wherein said cluster ion beam is boron hydride ions in the form of B18Hx+, wherein x is an integer and 0≦x≦22. 
     
     
         72 . The ion source as recited in  claim 69 , further including an electron exit aperture in said ionization chamber for exit of said electron beam, wherein said electron entrance aperture and said electron exit aperture are aligned and further including a beam dump, said beam dump disposed outside said ionization chamber and aligned with said electron entrance aperture and said electron exit aperture. 
     
     
         73 . The ion source as recited in  claim 69 , further including a second electron entrance aperture and a second source of electrons aligned with said second electron entrance aperture in said ionization chamber. 
     
     
         74 . The ion source as recited in  claim 69 , further including a vaporizer for vaporizing solid material in order to generate said boron hydride vapor. 
     
     
         75 . The ion source as recited in  claim 74 , wherein said solid material is octadecaborane B 18 H 22 . 
     
     
         81 . The ion source as recited in  claim 69 , further including an acceleration-deceleration electrode outside of said ion extraction aperture.