Load-monitor mwait

Abstract

Techniques are disclosed relating to suspending execution of a processor thread while monitoring for a write to a specified memory location. An execution subsystem may be configured to perform a load instruction that causes the processor to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified location. The load instruction may be a load-monitor instruction. The execution subsystem may be further configured to perform a wait instruction that causes the processor to suspend execution of a processor thread during at least a portion of an interval specified by the wait instruction and to resume execution of the processor thread at the end of the interval. The wait instruction may be a monitor-wait instruction. The processor may be further configured to resume execution of the processor thread in response to detecting a write to a memory location specified by a previous monitor instruction.

What is claimed is: 
     
         1 . An apparatus, comprising:
 an execution subsystem configured to perform a load instruction that causes the apparatus to retrieve data from a specified memory location and atomically begin monitoring for a write to the specified memory location.   
     
     
         2 . The apparatus of  claim 1 , wherein the load instruction is a load-monitor instruction of a particular instruction set architecture and the execution subsystem is a load/store unit. 
     
     
         3 . The apparatus of  claim 1 , wherein the apparatus is configured to:
 suspend execution of a thread based on a wait instruction; and   resume execution of the thread in response to detecting a write to the specified memory location.   
     
     
         4 . The apparatus of  claim 1 , wherein the apparatus is configured to begin monitoring for a write to the specified memory location before completion of the load instruction. 
     
     
         5 . The apparatus of  claim 1 , further comprising:
 a monitor unit; and   a cache comprising a plurality of cache lines;   wherein, to monitor for a write to the specified memory location, the monitor unit is configured to monitor a state of a cache line associated with the specified memory location.   
     
     
         6 . The apparatus of  claim 1 , further comprising:
 a monitor unit; and   an address bus;   wherein, to monitor for a write to the specified memory location, the monitor unit is configured to snoop the address bus.   
     
     
         7 . The apparatus of  claim 1 , wherein the execution subsystem comprises:
 a monitor unit; and   a load buffer;   wherein the execution subsystem is configured to speculatively perform the load instruction;   wherein the load buffer is configured to store the speculatively performed load; and   wherein, to atomically begin monitoring, the monitor unit is configured to begin monitoring for writes to the specified location while the speculatively performed load is stored in the load buffer.   
     
     
         8 . A apparatus, comprising:
 an execution subsystem configured to perform a wait instruction that causes the apparatus to suspend execution of a thread during at least a portion of an interval specified by the wait instruction;   wherein the apparatus is configured to resume execution of the thread upon an expiration of the interval.   
     
     
         9 . The apparatus of  claim 8 ,
 wherein the wait instruction is a monitor-wait instruction of a particular instruction set architecture; and   wherein, to specify the interval, the monitor-wait instruction specifies a register configured to store the interval.   
     
     
         10 . The apparatus of  claim 8 , wherein the wait instruction comprises a field that specifies the interval as an immediate value. 
     
     
         11 . The apparatus of  claim 8 , wherein the apparatus is further configured to resume execution of the thread in response to detecting a write to a memory location specified by a previous monitor instruction. 
     
     
         12 . The apparatus of  claim 11 , wherein the apparatus is further configured to indicate, after resuming the thread, whether the thread was resumed based on the interval or based on detecting the write. 
     
     
         13 . The apparatus of  claim 8 , wherein execution of the wait instruction causes the apparatus to suspend execution of the thread in response to the threshold being longer than a threshold interval. 
     
     
         14 . The apparatus of  claim 8 , wherein the apparatus is also configured to resume execution of the thread in response to:
 a trap request; or   a change in a processing state of the thread.   
     
     
         15 . The apparatus of  claim 8 ,
 wherein the execution subsystem, in response to receiving another instance of the wait instruction, is configured to perform a no-operation in response to one of a set of criteria being satisfied;   wherein the set of criteria is selected from the group consisting of: no monitor instruction is pending, a write to a memory location specified by a most recent monitor instruction is detected, and a trap occurs between the most recent monitor instruction and the other instance of the wait instruction.   
     
     
         16 . A method, comprising:
 an execution unit in a processor performing a load instruction, wherein the performing includes:
 the execution unit causing data specified by the load instruction to be retrieved from a memory location; and 
 monitoring for a store to the memory location; 
   wherein the causing data specified by the load instruction to be retrieved and beginning the monitoring are performed atomically.   
     
     
         17 . The method of  claim 16 , further comprising:
 the processor performing a wait instruction that specifies a suspension interval;   the processor suspending execution of a processor thread; and   the processor resuming execution of the thread in response to detecting an end of the suspension interval.   
     
     
         18 . The method of  claim 16 , wherein the load instruction is an atomic load-monitor instruction, and wherein the atomic load-monitor instruction is a most recently executed load-monitor instruction prior to the wait instruction. 
     
     
         19 . The method of  claim 16 , wherein the monitoring includes monitoring for a store by another processor thread to the memory location. 
     
     
         20 . The method of  claim 16 , wherein the monitoring includes monitoring a state of a cache line associated with the memory location.