Operating point management in multi-core architectures

Abstract

For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

What is claimed is: 
     
         1 . A processor comprising:
 a plurality of processor cores of the processor to operate at variable performance levels, wherein one of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time, and wherein the plurality of processor cores are in a same package;   logic of the processor to set one or more operating parameters for one or more of the plurality of processor cores;   logic of the processor to monitor activity of one or more of the plurality of processor cores; and   logic of the processor to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity,   wherein the logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set.   
     
     
         2 . The processor of  claim 1 , wherein the frequency for one or more of the plurality of processor cores is to be limited in response to a communicated frequency limit. 
     
     
         3 . The processor of  claim 1 , the plurality of processor cores to operate at variable frequencies, wherein one of the plurality of processor cores may operate at a frequency different than a frequency at which another one of the plurality of processor cores may operate. 
     
     
         4 . The processor of  claim 1 , the plurality of processor cores to operate at variable voltages. 
     
     
         5 . The processor of  claim 1 , wherein one or more of the plurality of processor cores may be in a sleep state when one or more others of the plurality of processor cores are active. 
     
     
         6 . The processor of  claim 1 , wherein the logic to monitor activity includes logic to identify a sleep state of one or more of the plurality of processor cores. 
     
     
         7 . The processor of  claim 1 , wherein the logic to set one or more operating parameters for one or more of the plurality of processor cores is to set one or more operating parameters based at least in part on performance. 
     
     
         8 . The processor of  claim 1 , wherein the logic to set one or more operating parameters for one or more of the plurality of processor cores is to set one or more operating parameters based at least in part on temperature. 
     
     
         9 . The processor of  claim 1 , wherein the logic to constrain power, in response to a low performance level of one of the plurality of processor cores, is to allow an increase in the frequency of one or more other ones of the plurality of processor cores. 
     
     
         10 . A processor comprising:
 a plurality of processor cores of the processor to operate at variable frequencies, wherein one of the plurality of processor cores may operate at one time at a frequency different than a frequency at which another one of the plurality of processor cores may operate at the one time, and wherein the plurality of processor cores are in a same package;   logic of the processor to set a frequency for one or more of the plurality of processor cores;   logic of the processor to monitor activity of one or more of the plurality of processor cores; and   logic of the processor to limit a frequency at which one or more of the plurality of processor cores may be set to constrain power of one or more of the plurality of processor cores.   
     
     
         11 . The processor of  claim 10 , wherein the frequency for one or more of the plurality of processor cores is to be limited in response to a communicated frequency limit. 
     
     
         12 . The processor of  claim 10 , the plurality of processor cores to operate at variable voltages. 
     
     
         13 . The processor of  claim 10 , wherein one or more of the plurality of processor cores may be in a sleep state when one or more others of the plurality of processor cores are active. 
     
     
         14 . The processor of  claim 10 , wherein the logic to monitor activity includes logic to identify a sleep state of one or more of the plurality of processor cores. 
     
     
         15 . The processor of  claim 10 , wherein the logic to set a frequency for one or more of the plurality of processor cores is to set the frequency based at least in part on performance. 
     
     
         16 . The processor of  claim 10 , wherein the logic to set a frequency for one or more of the plurality of processor cores is to set the frequency based at least in part on temperature. 
     
     
         17 . The processor of  claim 10 , wherein the logic to limit a frequency at which one or more of the plurality of processor cores may be set, in response to a low performance level of one of the plurality of processor cores, is to allow an increase in the frequency of one or more other ones of the plurality of processor cores. 
     
     
         18 . A method comprising:
 operating a plurality of processor cores of a processor at variable performance levels, wherein one of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time, wherein the plurality of processor cores are in a same package, and wherein the operating includes setting one or more operating parameters for one or more of the plurality of processor cores;   monitoring activity of one or more of the plurality of processor cores; and   constraining power of one or more of the plurality of processor cores based at least in part on the monitored activity,   wherein the constraining power includes limiting a frequency at which one or more of the plurality of processor cores may be set.   
     
     
         19 . The method of  claim 18 , wherein the frequency for one or more of the plurality of processor cores is limited in response to a communicated frequency limit. 
     
     
         20 . The method of  claim 18 , wherein the operating the plurality of processor cores includes operating the plurality of processor cores at variable frequencies, wherein one of the plurality of processor cores may operate at a frequency different than a frequency at which another one of the plurality of processor cores may operate. 
     
     
         21 . The method of  claim 18 , wherein the operating the plurality of processor cores includes operating the plurality of processor cores at variable voltages. 
     
     
         22 . The method of  claim 18 , wherein one or more of the plurality of processor cores may be in a sleep state when one or more others of the plurality of processor cores are active. 
     
     
         23 . The method of  claim 18 , wherein the monitoring activity includes monitoring a sleep state of one or more of the plurality of processor cores. 
     
     
         24 . The method of  claim 18 , wherein the setting includes setting one or more operating parameters based at least in part on performance. 
     
     
         25 . The method of  claim 18 , wherein the setting includes setting one or more operating parameters based at least in part on temperature. 
     
     
         26 . The method of  claim 18 , comprising, in response to a low performance level of one of the plurality of processor cores, allowing an increase in the frequency of one or more other ones of the plurality of processor cores.