Semiconductor memory devices and methods of fabricating the same

Abstract

Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a plurality of spaces, treating the plurality of diode patterns to form a plurality of semiconductor patterns in each of the plurality of spaces, removing portions of the plurality of semiconductor patterns to form a recess in each of the plurality of spaces, treating the of the plurality of semiconductor patterns to form a plurality of diodes in each of the plurality of spaces, forming a bottom electrode on each of the plurality of diodes, forming a plurality of memory elements on each of the bottom electrodes, and forming a plurality of upper interconnection lines on the plurality of memory elements.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 a substrate including a plurality of active regions separated by a plurality of device isolation patterns;   a plurality of diodes on the plurality of active regions, adjacent ones of the plurality of diodes separated by the plurality of device isolation patterns in one direction;   a plurality of bottom electrodes on the plurality of diodes, adjacent ones of the plurality of bottom electrodes separated by the plurality of device isolation patterns;   a plurality of memory elements on the plurality of bottom electrodes adjacent ones of the plurality of memory elements separated by a plurality of interlayer insulating patterns; and   a plurality of upper interconnection lines on the plurality of memory elements.   
     
     
         2 . The memory device of  claim 1 , wherein the plurality of device isolation patterns and a plurality of field isolation patterns are aligned. 
     
     
         3 . The memory device of  claim 1 , wherein the plurality of diodes are separated by the plurality of device isolation patterns in one direction and a plurality of gap-fill patterns in the other directions. 
     
     
         4 . The memory device of  claim 1 , wherein the plurality of diodes are separated by a plurality of mold patterns in one direction and a plurality of gap-fill patterns in the other directions. 
     
     
         5 . A memory device, comprising:
 a plurality of pairs of diodes, each pair of the plurality of pairs of diodes having a “V-shape”.   
     
     
         6 . The memory device of  claim 5 , wherein each diode of the plurality of pairs of diodes having substantially parallel opposite side walls. 
     
     
         7 . The memory device of  claim 6 , wherein the substantially parallel opposite side walls are the inside and outside sidewalls.