Built off testing apparatus

Abstract

A built off testing apparatus coupled between a semiconductor device and an external testing apparatus to test a semiconductor device. The built off testing apparatus can include a frequency multiplying unit to generate a test clock frequency by multiplying the frequency of a clock input by the external testing apparatus according to the operation speed of the semiconductor device, an instruction decoding unit to generate test information by decoding test signals input by the external testing apparatus according to the test clock frequency, and a test execution unit to test the semiconductor device according to the test information, and can determine whether the semiconductor device is failed or not based on test data output by the semiconductor device, and can transmit resulting data to the external testing apparatus.

What is claimed is: 
     
         1 . A method of testing a semiconductor device, comprising:
 generating a test signal frequency from a clock frequency of an external testing apparatus according to an operation speed of the semiconductor device;   generating test information from a test signal of the external testing apparatus according to the test signal frequency; and   inputting the test information to the semiconductor device according to the test signal frequency to determine whether the semiconductor device is failed.   
     
     
         2 . The method of  claim 1 , further comprising:
 receiving result data from the semiconductor device based on the input test information; and   transmitting the result data to the external testing apparatus according to the clock frequency of the external testing apparatus.   
     
     
         3 . The method of  claim 1 , further comprising:
 comparing output values of the semiconductor device to expected output values according to the test signal frequency to determine whether the semiconductor device is failed.   
     
     
         4 . The method of  claim 1 , wherein the generating a test signal frequency comprises multiplying the clock signal according to the operating speed of the semiconductor device. 
     
     
         5 . The method of  claim 1 , wherein the generating test information comprises decoding testing information of the external testing apparatus according to the test signal frequency.