Programming technique for reducing program disturb in stacked memory structures

Abstract

A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set.

1 . A method of operating a memory including a stacked memory structure, wherein multibit addresses map to corresponding memory cells disposed in a plurality of layers, comprising:
 responsive to a program instruction to store data in a set of memory cells corresponding to a particular multibit address, executing a program operation limited to memory cells in a first set of layers that include memory cells in said set of memory cells, said first set including subsets of one or more of the layers in said first set of layers, where the subsets of the first set are separated from other subsets of the first set by at least two layers that are not members of the first set, and   then completing programming if necessary of remaining memory cells in said set of memory cells.   
     
     
         2 . The method of  claim 1 , wherein the program operation causes one or more memory cells in the first set of layers to change to a programmed state and to inhibit changes in state in memory cells to memory cells in a second set of layers that include memory cells in said set of memory cells;
 the program operation including applying a bias arrangement that includes:
 (i) a program voltage applied to the one or more of the memory cells in the first set of layers, and 
 (ii) an inhibit voltage applied to all memory cells in the second set of layers; and 
   if data to be stored requires a change of state of memory cells in the second set of layers, then executing another program operation, to cause one or more memory cells in the second set of layers to change to a programmed state.   
     
     
         3 . The method of  claim 2 , wherein said another program operation includes applying a second bias arrangement that includes:
 (i) a program voltage applied to the one or more of the memory cells in the second set, and   (ii) an inhibit voltage applied to all memory cells in the first set of the plurality of layers.   
     
     
         4 . The method of  claim 2 , wherein said first mentioned program operation is configured so that the first set includes a first subset including a first pair of layers and a third subset including a third pair of layers and the second set includes a first subset including a second pair of layers, and wherein the first pair of layers and the third pair of layers are separated by the second pair of layers. 
     
     
         5 . The method of  claim 4 , wherein at least one memory cell in the first pair of layers and at least one memory cell in the third pair of layers are programmed during the first mentioned program operation. 
     
     
         6 . The method of  claim 4 , wherein the second set includes a second subset including a fourth pair of layers, the second pair of layers and the fourth pair of layers being separated by the third pair of layers, and in which at least one memory cell in the second pair of layers and at least one memory cell in the fourth pair of layers are programmed during the second mentioned another program operation. 
     
     
         7 . The method of  claim 1 , wherein the program bias arrangement includes the inhibit voltage applied to memory cells in the corresponding memory cells in the first set of the plurality of layers for which no change in state is needed to store the data. 
     
     
         8 . The method of  claim 1 , further including identifying memory cells in the corresponding memory cells for which a change in state is needed to store the data, and if possible assigning memory cells to the first set of the plurality of layers so that it includes all of the identified memory cells. 
     
     
         9 . The method of  claim 1 , wherein the plurality of layers includes said first set of layers, a second set of layers and a third set of layers, the layers in the second set of layers being separated by one layer in the third set of layers and one layer in the first set, and including:
 after applying said first mentioned program operation, applying a second program operation for cells in the second set, and then applying a third program operation for cells in the third set.   
     
     
         10 . A memory comprising:
 a stacked memory structure with layers of memory cells, wherein multibit addresses map to corresponding memory cells disposed in a plurality of layers;   circuitry coupled to the stacked memory structure, the logic and control circuitry configured to:   respond to a program instruction to store data in a set of memory cells corresponding to a particular multibit address, by executing a program operation limited to memory cells in a first set of layers that include memory cells in said set of memory cells, said first set including subsets of one or more of the layers in said first set of layers, where the subsets of the first set are separated from other subsets of the first set by at least two layers that are not members of the first set, and then completing programming if necessary of remaining memory cells in said set of memory cells   
     
     
         11 . The memory of  claim 10 , wherein the program operation causes one or more memory cells in the first set of layers to change to a programmed state and to inhibit changes in state in memory cells in a second set of layers in the plurality of layers;
 the program operation including applying a bias arrangement that includes:
 (i) a program voltage applied to the one or more of the memory cells in the first set of layers, and 
 (ii) an inhibit voltage applied to all memory cells in the second set of layers; and 
   the logic and control circuitry responsive to the program instruction to program data at the particular multibit address being configured to, if data to be stored requires a change of state of memory cells in the second set of layers, then executing another program operation, to cause one or more memory cells in the second set of layers to change to a programmed state.   
     
     
         12 . The memory of  claim 11 , wherein said another program operation includes applying a second bias arrangement that includes:
 (i) a program voltage applied to the one or more of the memory cells in the second set, and   (ii) an inhibit voltage applied to all memory cells in the first set of the plurality of layers.   
     
     
         13 . The memory of  claim 12 , wherein said first mentioned program operation is configured so that the first set includes a first subset including a first pair of layers and a third subset including a third pair of layers and the second set includes a first subset including a second pair of layers, and wherein the first pair of layers and the third pair of layers are separated by the second pair of layers. 
     
     
         14 . The memory of  claim 13 , wherein at least one memory cell in the first pair of layers and at least one memory cell in the third pair of layers are programmed during the first mentioned program operation. 
     
     
         15 . The memory of  claim 13 , wherein the second set includes a second subset including a fourth pair of layers, the second pair of layers and the fourth pair of layers being separated by the third pair of layers, and in which at least one memory cell in the second pair of layers and at least one memory cell in the fourth pair of layers are programmed during said another program operation. 
     
     
         16 . The memory of  claim 11 , wherein the program bias arrangement includes the inhibit voltage applied to memory cells in the set of corresponding memory cells in the first set of the plurality of layers for which no change in state is needed to store the data. 
     
     
         17 . The memory of  claim 11 , the logic and control circuitry responsive to the program instruction to program data at the particular multibit address being configured to identify memory cells in the corresponding memory cells for which a change in state is needed to store the data, and if possible assign memory cells to the first set of the plurality of layers so that it includes all of the identified memory cells. 
     
     
         18 . The memory of  claim 11 , wherein the plurality of layers includes said first set of layers, a second set of layers and a third set of layers, the layers in the second set of layers being separated by one layer in the third set of layers and one layer in the first set, and including:
 the logic and control circuitry responsive to the program instruction to program data at the particular multibit address being configured to, after applying said first mentioned program operation, apply a second program operation for cells in the second set, and then apply a third program operation for cells in the third set.   
     
     
         19 . A memory comprising:
 a stacked memory structure with layers of memory cells;   circuitry coupled to the stacked memory structure, the circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address, the circuitry configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence, where each iteration includes applying program voltages to target cells in a selected one of the plurality of sets, inhibit voltages to remaining cells in said selected one of the plurality of sets, and inhibit voltages to all of the cells in others of the plurality of sets.   
     
     
         20 . The memory of  claim 19 , wherein the sets in the plurality of sets include subsets of cells in the stack, including a first subset in a given set and a second subset in the given set, where assignment of cells to the first and second subsets insures that no cells in the first subset are disposed in layers separated by only one layer from layers including a cell in the second subset. 
     
     
         21 . The memory of  claim 19 , wherein assignment groups cells in sets so no cell having inhibit voltages applied is in a layer of the stack between two layers in which cells are having programming applied. 
     
     
         22 . The memory of  claim 19 , wherein assignment groups cells in sets so no cell having programming voltages applied is in a layer of the stack adjacent any layer including a cell that is having programming voltages applied. 
     
     
         23 . The memory of  claim 22 , wherein assignment groups cells in sets so no cell having inhibit voltages applied is in a layer of the stack between two layers in which cells are having programming applied. 
     
     
         24 . The memory of  claim 19 , wherein the group program operation includes logic to skip a selected set if there are no target cells in the set.