Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 gate electrodes on a semiconductor substrate;   spacers on side surfaces of the gate electrodes;   capping patterns on the gate electrodes; and   a metal contact between the gate electrodes,   wherein a width of each of the capping patterns is greater than a width of each of the gate electrodes.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a gate insulating layer disposed between the semiconductor substrate and the gate electrodes. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the capping patterns cover upper surfaces of the gate electrodes and at least some of the spacers. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising etch stopper patterns covering the spacers and disposed between the spacers and the metal contact. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the gate electrodes comprise at least one of aluminum, titanium nitride and tantalum nitride. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the capping patterns comprise a silicon oxide layer. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising a silicide layer between the semiconductor substrate and the metal contact. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising mask patterns on the capping patterns, wherein the mask patterns extend in one direction to cover the capping patterns and have a width greater than the width of the capping patterns. 
     
     
         9 . The semiconductor device of  claim 8 , wherein an upper surface of the metal contact is at the same level as an upper surface of at least some of the mask patterns. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the mask patterns comprise a recess pattern having an upper surface which is lower than the upper surface of the metal contact. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the metal contacts disposed at opposite sides of the recess pattern are connected to each other on the recess pattern. 
     
     
         12 . The semiconductor device of  claim 1 , wherein the gate pattern comprises an aluminum layer and an aluminum oxide layer on the aluminum layer. 
     
     
         13 . The semiconductor device of  claim 1 , wherein the spacers disposed on first side surfaces of the gate electrodes have upper portions which are recessed.