Method of fabricating semiconductor device

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

What is claimed is: 
     
         1 . A semiconductor device including a MISFET, comprising:
 a semiconductor substrate;   a first semiconductor region of a first conductivity type formed in the semiconductor substrate;   a second semiconductor region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate and formed over the first semiconductor region;   a third semiconductor region of the first conductivity type formed in the semiconductor substrate and formed over the second semiconductor region;   a first trench formed in the semiconductor substrate such that a bottom of the first trench reaches at the first semiconductor region;   a gate insulating film of the MISFET formed on the first trench;   a gate electrode of the MISFET formed in the first trench and formed on the gate insulating film;   a first insulating film formed over the gate insulating film, the gate electrode and the third semiconductor region; and   a conductive film formed over the first insulating film and electrically connected to the second semiconductor region and the third semiconductor region,   wherein a side surface of the first trench including a first portion and a second portion arranged near a surface of the semiconductor substrate rather than the first portion such that the second portion has a sloping shape rather than first portion,   wherein an upper surface of the gate insulating film is arranged at a position lower than the second portion,   wherein the third semiconductor region is serving as a source region of the MISFET,   wherein the second semiconductor region is serving as a channel forming region of the MISFET, and   wherein the first semiconductor region is serving as a drain region of the MISFET.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the gate insulating film are not formed over the second portion.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein the first insulating film is formed of a laminate film.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the laminate film includes a silicon oxide film and a BPSG film.   
     
     
         5 . The semiconductor device according to  claim 1 ,
 wherein the MISFET is an n-type MISFET,   wherein the first conductivity type is an n-type, and   wherein the second conductivity type is a p-type.