Apparatus and Methods for Peak Power Management in Memory Systems

Abstract

Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system.

What is claimed is: 
     
         1 . A method for managing power in a memory system having a controller and nonvolatile memory array, the method comprising:
 prior to execution of each command with respect to the memory array, receiving a request for execution of such command with respect to the memory array; and   in response to receipt of each request for each command, allowing or withholding execution of such command with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system.   
     
     
         2 . The method of  claim 1 , wherein the memory array is formed within multiple die and/or multiple planes that are accessible in parallel. 
     
     
         3 . The method of  claim 1 , wherein allowing or withholding execution of each command with respect to the memory array is further based on whether such command has a type of command that has been previously executed more than a predetermined threshold number of times. 
     
     
         4 . The method of  claim 1 , wherein allowing or withholding execution of each command with respect to the memory array is further based on a configurable decision matrix describing necessary delays between execution of each different type of command or a combination of commands. 
     
     
         5 . The method of  claim 1 , wherein each request for execution of a command with respect to the memory array is received by a power arbitration unit of the controller. 
     
     
         6 . The method of  claim 1 , further comprising: prior to execution of each command with respect to the controller, receiving a request for execution of such command with respect to the controller; and in response to receipt of each request for execution of each command with respect to the controller, allowing or withholding execution of such command with respect to the controller based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system. 
     
     
         7 . The method of  claim 6 , wherein each request that is received with respect to the controller is received with respect to an error correction coding (ECC) module an encryption module of the controller. 
     
     
         8 . A memory system comprising:
 a nonvolatile memory array for storing data;   a flash protocol sequencer (FPS) for accessing the memory array and prior to such accessing, requesting permission from a power arbitration unit to access such memory array;   the power arbitration unit (PAU) for allowing or withholding permission to the FPS for accessing the memory array, wherein the PAU is configured to determine whether to allow or withhold based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system.   
     
     
         9 . The memory system of  claim 8 , wherein the memory array is formed within multiple die and/or multiple planes that are accessible in parallel. 
     
     
         10 . The memory system of  claim 8 , wherein allowing or withholding execution of each command with respect to the memory array is further based on whether such command has a type of command that has been previously executed more than a predetermined threshold number of times. 
     
     
         11 . The memory system of  claim 8 , wherein allowing or withholding execution of each command with respect to the memory array is further based on a configurable decision matrix describing necessary delays between execution of each different type of command or a combination of commands.