Semiconductor device

Abstract

A semiconductor device includes a word line, a bit line, a power supply node, a memory element that includes at least first and second regions that form a PN junction between the bit lie and the power supply node, and a third region that forms a PN junction with the second region and a capacitor that includes a first electrode provided independently from the second region of the memory element and electrically connected to the second region of the memory element, and a second electrode connected to the word line.

1 . A semiconductor device comprising:
 a word line;   a bit line;   a power supply node;   a memory element that comprises at least first and second regions that form a PN junction between said bit line and said power supply node, and a third region that forms a PN junction with said second region; and   a capacitor that comprises a first electrode provided independently from said second region of said memory element and electrically connected to said second region of said memory element, and a second electrode connected to said word line.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein said memory element is a thyristor that forms a PN junction with said third region and that comprises a fourth region separated from said second region, and said bit line is electrically connected to said fourth region. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein said memory element is a bipolar transistor, and said bit line is electrically connected to said third region. 
     
     
         4 . The semiconductor device according to  claim 1  setting a voltage of said word line to an intermediate voltage between a selection level and a non-selection level from said selection-level voltage and fixing a voltage of said bit line to a non-selection-level voltage, and setting said word line voltage to a non-selection-level voltage from said intermediate voltage after fixing said bit line voltage to said non-selection-level voltage at the end of read and/or write operation(s) when activating said bit line and said word line and performing said read and/or write operation(s). 
     
     
         5 . The semiconductor device according to  claim 1 , wherein first and second power supply voltages are supplied to said semiconductor device from the outside, and said first power supply voltage is supplied to said power supply node. 
     
     
         6 . The semiconductor device according to  claim 5 , wherein said word line is controlled by a voltage within a range between said first and said second power supply voltages. 
     
     
         7 . The semiconductor device according to  claim 5 , wherein said word line is maintained at said first power supply voltage when unselected. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein said word line is controlled to be at a just intermediate voltage between a voltage after high-level data has been written and a voltage after low-level data has been written to said second region of said memory element when unselected. 
     
     
         9 . The semiconductor device according to  claim 8 , wherein said non-selection-level voltage of said word line has such a temperature characteristic that a temperature characteristic of a forward voltage of said PN junction between said first and said second regions of said memory element is compensated. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein said first power supply node is connected to said first region of said memory element directly or via a switch. 
     
     
         11 . The semiconductor device according to  claim 1  comprising:
 a plurality of said word lines wired in a first direction; 
 a plurality of said bit lines wired in a second direction that intersects said first direction; 
 a plurality of memory cells provided corresponding to each of intersections between said plurality of word lines and said plurality of bit lines, each of said memory cells comprising: said memory element connected to each corresponding one of said bit lines and said capacitor having said second electrode connected to said word line corresponding to said first electrode connected to said second region of said memory element; 
 a plurality of word line drivers each of which drives each of said plurality of word lines; and 
 a plurality of sense amplifiers each of which is connected to each of said plurality of bit lines, amplifies a signal of a corresponding bit line during a read operation, and drives said corresponding bit line during a write operation.