Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material

Abstract

A semiconductor device includes a first metallization layer positioned above a substrate of the semiconductor device, the metallization layer including a dielectric material and a copper-containing metal region embedded in the dielectric material. The semiconductor device also includes a conductive barrier layer positioned along substantially an entirety of an interface between the copper-containing metal region and the dielectric material, the conductive barrier layer including a copper/silicon compound that is in direct contact with the dielectric material along substantially the entirety of the interface.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 a first metallization layer positioned above a substrate of said semiconductor device, said metallization layer comprising a dielectric material and a copper-containing metal region embedded in said dielectric material; and   a conductive barrier layer positioned along substantially an entirety of an interface between said copper-containing metal region and said dielectric material, said conductive barrier layer comprising a copper/silicon compound that is in direct contact with said dielectric material along substantially said entirety of said interface.   
     
     
         22 . The semiconductor device of  claim 21 , further comprising a via connecting said copper-containing metal region with a second metal region formed in a second metallization layer that is positioned below said first metallization layer, wherein said conductive barrier layer extends to a bottom of said via so as to separate said via from said second metal region. 
     
     
         23 . The semiconductor device of  claim 22 , wherein said via is embedded in said dielectric material of said first metallization layer, said copper/silicon compound comprising said conductive barrier layer being in direct contact with said dielectric material along substantially said entirety of a sidewall interface between said via and said dielectric layer. 
     
     
         24 . The semiconductor device of  claim 21 , wherein said conductive barrier layer comprises a silicon layer disposed along at least a portion of said interface. 
     
     
         25 . The semiconductor device of  claim 21 , wherein an atomic percent concentration of any non-silicon species and any non-copper species comprising said conductive barrier layer is less than 5 atomic percent relative to a combined atomic percent concentration of silicon and copper comprising said conductive barrier layer. 
     
     
         26 . The semiconductor device of  claim 21 , further comprising a cap layer positioned above said dielectric material and said copper-containing metal region. 
     
     
         27 . The semiconductor device of  claim 21 , wherein said copper/silicon compound comprises copper silicide. 
     
     
         28 . The semiconductor device of  claim 21 , wherein said dielectric material comprises a low-k dielectric material having a relative permittivity of 3.0 or less. 
     
     
         29 . A semiconductor device, comprising:
 a layer of dielectric material positioned above a semiconductor substrate;   and interconnect structure embedded in said layer of dielectric material, said interconnect structure comprising:
 a metal region; and 
 a copper silicide barrier layer positioned between said layer of dielectric material and said metal region, said copper silicide barrier layer extending along substantially an entirety of an interface between said metal region and said layer of dielectric material, wherein said copper silicide barrier layer is in direct contact with said layer of dielectric material along substantially said entirety of said interface. 
   
     
     
         30 . The semiconductor device of  claim 29 , wherein said metal region comprises copper. 
     
     
         31 . The semiconductor device of  claim 29 , wherein said interconnect structure comprises at least one of a conductive line and a conductive via. 
     
     
         32 . The semiconductor device of  claim 29 , further comprising a dielectric cap layer positioned above an upper surface of said layer of dielectric material and above an upper surface of said interconnect structure. 
     
     
         33 . The semiconductor device of  claim 29 , wherein said interconnect structure and said layer of dielectric material comprise a first metallization layer of a metallization system of said semiconductor device, said semiconductor device further comprising a second metallization layer of said metallization system positioned below said first metallization layer. 
     
     
         34 . The semiconductor device of  claim 33 , wherein said second metallization layer comprises a second layer of dielectric material and a second metal region embedded in said second layer of dielectric material, said interconnect structure directly contacting said second metal region. 
     
     
         35 . The semiconductor device of  claim 34 , wherein said copper silicide barrier layer extends along an interface between said interconnect structure and said second metal region. 
     
     
         36 . The semiconductor device of  claim 34 , further comprising a dielectric cap layer positioned between said first and second metallization layers. 
     
     
         37 . The semiconductor device of  claim 34 , wherein at least one of said layer of dielectric material and said second layer of dielectric material comprises a low-k dielectric material having a relative permittivity of 3.0 or less. 
     
     
         38 . The semiconductor device of  claim 34 , wherein said second metal region comprises copper.