Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby

Abstract

Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) synthesizing a netlist from the functional IC design that meets the target clock rate, (4) determining a performance/power ratio from the netlist, (5) attempting to increase the performance/power ratio by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, and (6) implementing a layout of the IC from the netlist.

What is claimed is: 
     
         1 . A method of designing an integrated circuit, comprising:
 generating a functional integrated circuit design;   determining a target clock rate for said functional integrated circuit design;   synthesizing a netlist from said functional integrated circuit design that meets said target clock rate;   determining a performance/power ratio from said netlist;   attempting to increase said performance/power ratio by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in said netlist; and   implementing a layout of said integrated circuit from said netlist.   
     
     
         2 . The method as recited in  claim 1  further comprising determining a target area for said functional integrated circuit design. 
     
     
         3 . The method as recited in  claim 1  further comprising determining a target power consumption for said functional integrated circuit design. 
     
     
         4 . The method as recited in  claim 1  further comprising determining whether said integrated circuit is to employ voltage scaling or adaptive voltage scaling. 
     
     
         5 . The method as recited in  claim 1  wherein said attempting comprises attempting to increase said performance/power ratio by changing all of said speed, said area and said power consumption in said at least some noncritical paths in said netlist. 
     
     
         6 . The method as recited in  claim 1  wherein said attempting comprises attempting to increase said performance/power ratio by changing said at least one of said speed, said area and said power consumption in all of said noncritical paths in said netlist. 
     
     
         7 . The method as recited in  claim 1  wherein said attempting is carried out only with respect to true noncritical paths in said netlist. 
     
     
         8 . An integrated circuit designed by the method as recited in  claim 1 . 
     
     
         9 . A method of designing an integrated circuit, comprising:
 generating a functional integrated circuit design;   determining a target clock rate for said functional integrated circuit design;   determining a target area for said functional integrated circuit design;   determining a target power consumption for said functional integrated circuit design;   determining whether said integrated circuit is to employ voltage scaling or adaptive voltage scaling;   synthesizing a netlist from said functional integrated circuit design that meets said target clock rate;   determining a performance/power ratio from said netlist;   attempting to increase said performance/power ratio by changing all of said speed, said area and said power consumption in said at least some noncritical paths in said netlist; and   implementing a layout of said integrated circuit from said netlist.   
     
     
         10 . The method as recited in  claim 9  wherein said attempting comprises attempting to increase said performance/power ratio by changing said at least one of said speed, said area and said power consumption in all of said noncritical paths in said netlist. 
     
     
         11 . The method as recited in  claim 9  wherein said attempting is carried out only with respect to true noncritical paths in said netlist. 
     
     
         12 . An integrated circuit designed by the method as recited in  claim 9 . 
     
     
         13 . An integrated circuit, comprising:
 functional circuitry located in at least one drive voltage domain;   at least one PVT monitor and at least one thermal monitor located in said at least one domain;   a voltage management unit configured to receive output signals from said at least one PVT monitor and said at least one thermal monitor and determine at least one drive voltage for said at least one domain based thereon; and   a regulator coupled to said voltage management unit and configured to provide said at least one drive voltage.   
     
     
         14 . The integrated circuit as recited in  claim 13  further comprising at least one critical path detector located in said at least one domain, said voltage management unit further configured to receive output signals from said at least one critical path monitor and determine said at least one drive voltage based thereon. 
     
     
         15 . The integrated circuit as recited in  claim 13  wherein said regulator includes an integrated regulator. 
     
     
         16 . The integrated circuit as recited in  claim 13  wherein said regulator includes an integrated power controller. 
     
     
         17 . The integrated circuit as recited in  claim 13  wherein said regulator includes a commercial regulator interface. 
     
     
         18 . The integrated circuit as recited in  claim 13  wherein said regulator includes a system-specific interface. 
     
     
         19 . The integrated circuit as recited in  claim 13  further comprising a host processor coupled to said voltage management unit.