Semiconductor chip and a semiconductor package having a package on package (pop) structure including the semiconductor chip

Abstract

A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

What is claimed is: 
     
         1 . A semiconductor chip, comprising:
 a substrate;   a first data pad arranged on the substrate; and   a first control/address pad arranged on the substrate,   wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.   
     
     
         2 . The semiconductor chip of  claim 1 , wherein the semiconductor chip comprises a logic chip. 
     
     
         3 . The semiconductor chip of  claim 1 , further comprising a second data pad and a second control/address pad,
 wherein the first and second data pads are arranged in adjacent edge regions of the substrate, and   the first and second control/address pads are arranged opposite to the first and second data pads, respectively.   
     
     
         4 . The semiconductor chip of  claim 1 , further comprising a second data pad and a second control/address pad, and
 wherein the first and second data pads are arranged side by side in the same edge region of the substrate.   
     
     
         5 . The semiconductor chip of  claim 1 , further comprising a second data pad and a second control/address pad, and
 wherein the first and second data pads are arranged in opposite edge regions of the substrate.   
     
     
         6 . The semiconductor chip of  claim 1 , wherein the first data pad and the first control/address pad form a channel. 
     
     
         7 . A semiconductor package having a Package On Package (POP) structure, comprising:
 a first package comprising a first substrate and a first semiconductor chip mounted on the first substrate;   a second package disposed on the first package and comprising a second substrate and a second semiconductor chip mounted on the second substrate;   a first sealant for sealing the first semiconductor chip to the first substrate;   a second sealant for sealing the second semiconductor chip to the second substrate; and   at least one substrate interconnection member for connecting the first substrate and the second substrate,   wherein a first data pad is arranged in an edge region of the first semiconductor chip, and a first control/address pad is arranged in a center region of the first semiconductor chip.   
     
     
         8 . The semiconductor package of  claim 7 , wherein the first semiconductor chip comprises a logic chip, and
 the second semiconductor chip comprises a memory chip.   
     
     
         9 . The semiconductor package of  claim 7 , further comprising a second data pad and a second control/address pad,
 wherein the first and second data pads are arranged in adjacent edge regions of the first semiconductor chip, and   the first and second control/address pads are arranged in the center region of the semiconductor chip, opposite to the first and second data pads, respectively.   
     
     
         10 . The semiconductor package of  claim 9 , wherein the substrate interconnection members are arranged in three rows in respective first and second opposite edge regions of the first substrate, and the substrate interconnection members are arranged in two rows in the respective third and fourth opposite edge regions of the first substrate, wherein the first and second data pads are arranged along the first opposite edge region. 
     
     
         11 . The semiconductor package of  claim 7 , further comprising a second data pad and a second control/address pad, and
 wherein the first and second data pads are arranged side by side in the same edge region of the first semiconductor chip.   
     
     
         12 . The semiconductor package of  claim 11 , wherein the substrate interconnection members are arranged in three rows in an edge region of the first substrate in which the first and second data pads are arranged, and the substrate interconnection members are arranged in two rows in three other respective edge regions of the first substrate. 
     
     
         13 . The semiconductor package of  claim 7 , further comprising a second data pad and a second control/address pad, and
 wherein the first and second data pads are arranged in opposite edge regions of the first semiconductor chip.   
     
     
         14 . The semiconductor package of  claim 13 , wherein the substrate interconnection members are arranged in three rows in respective edge regions of the first substrate in which the first and second data pads are arranged, and the substrate interconnection members are not arranged in the other edge regions of the first substrate. 
     
     
         15 . The semiconductor package of  claim 7 , wherein the first data pad and the first control/address pad form a channel. 
     
     
         16 . A semiconductor package, comprising:
 a first semiconductor chip;   a data pad disposed on a first surface of the first semiconductor chip; and   a control/address pad disposed on the first surface of the first semiconductor chip,   wherein the data pad is disposed in an edge portion of the first semiconductor chip and the control/address pad is disposed in a center portion of the first semiconductor chip.   
     
     
         17 . The semiconductor package of  claim 16 , further comprising a second semiconductor chip facing a second surface of the first semiconductor chip. 
     
     
         18 . The semiconductor package of  claim 17 , wherein the second semiconductor chip includes a memory chip. 
     
     
         19 . The semiconductor package of  claim 18 , wherein the memory chip includes a double-data rate synchronous dynamic random access memory. 
     
     
         20 . The semiconductor package of  claim 16 , wherein the data pad and the control/address pad form a channel.