Memory system with a programmable refresh cycle

Abstract

A memory system with a programmable refresh cycle including a memory device. The memory device includes refresh circuitry in communication with a memory array and with a memory controller. The refresh circuitry is configured for receiving a refresh command from the memory controller and for refreshing a number of memory cells in the memory device in response to receiving the refresh command. A refresh cycle time of the refresh command is programmable. The memory device also includes a programmable refresh cycle mode register in communication with the refresh circuitry. Contents of the programmable refresh cycle mode register indicate the refresh cycle time of the refresh command.

What is claimed is: 
     
         1 . A memory device comprising:
 refresh circuitry in communication with a memory array and with a memory controller, the refresh circuitry configured for receiving a refresh command from the memory controller and for refreshing a number of memory cells in the memory device in response to receiving the refresh command, wherein a refresh cycle time of the refresh command is programmable; and   a programmable refresh cycle mode register in communication with the refresh circuitry, wherein contents of the programmable refresh cycle mode register indicate the refresh cycle time of the refresh command.   
     
     
         2 . The memory device of  claim 1 , wherein the memory device further comprises the memory array. 
     
     
         3 . The memory device of  claim 1 , wherein the contents of the programmable refresh cycle mode register are programmed by the memory controller. 
     
     
         4 . The memory device of  claim 1 , wherein the number of memory cells refreshed in response to receiving the refresh command is programmed by the memory controller. 
     
     
         5 . The memory device of  claim 1 , wherein the memory device is a direct random access memory (DRAM) device. 
     
     
         6 . The memory device of  claim 1 , wherein the cells are grouped into memory banks and the memory cells refreshed belong to a subset of the groups of memory banks. 
     
     
         7 . The memory device of  claim 1 , wherein the refreshing is staggered in time between at least two of the memory cells being refreshed. 
     
     
         8 . A memory module comprising:
 a memory device, the memory device comprising:
 refresh circuitry in communication with a memory array and with a memory controller, the refresh circuitry configured for receiving a refresh command from the memory controller and for refreshing a number of memory cells in the memory device in response to receiving the refresh command, wherein a refresh cycle time of the refresh command is programmable; and 
 a programmable refresh cycle mode register in communication with the refresh circuitry, wherein contents of the programmable refresh cycle mode register indicate the refresh cycle time of the refresh command. 
   
     
     
         9 . The memory module of  claim 8 , wherein the memory device further comprises the memory array. 
     
     
         10 . The memory module of  claim 8 , wherein the contents of the programmable refresh cycle mode register are programmed by the memory controller. 
     
     
         11 . The memory module of  claim 8 , wherein the number of memory cells refreshed in response to receiving the refresh command is programmed by the memory controller. 
     
     
         12 . The memory module of  claim 8 , wherein the memory device is a direct random access memory (DRAM) device. 
     
     
         13 . The memory module of  claim 8 , wherein the cells are grouped into memory banks and the memory cells refreshed belong to a subset of the groups of memory banks. 
     
     
         14 . The memory module of  claim 8 , wherein the refreshing is staggered in time between at least two of the memory cells being refreshed.