Semiconductor device and method of fabricating the same

Abstract

A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate;   first and second stress-generating epitaxial regions on the substrate and spaced apart from each other;   a channel region on the substrate and positioned between the first and second stress-generating epitaxial regions, the channel region being an epitaxial layer grown under stress of the first and second stress-generating epitaxial regions; and   a gate electrode on the channel region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first and second stress-generating epitaxial regions impart a stress on the channel region. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the channel region is grown using the underlying substrate as a seed layer. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the channel region is grown further using the first and second stress-generating epitaxial regions as a seed layer. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the first and second stress-generating epitaxial regions impart a compressive stress on the channel region. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the first and second stress-generating epitaxial regions comprise SiGe. 
     
     
         7 . The semiconductor device of  claim 5 , wherein the first and second stress-generating epitaxial regions comprise source and drain regions and wherein the semiconductor device comprises a PMOS transistor. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the first and second stress-generating epitaxial regions impart a tensile stress on the channel region. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the first and second stress-generating epitaxial regions comprise SiC. 
     
     
         10 . The semiconductor device of  claim 8 , wherein the first and second stress-generating epitaxial regions comprise source and drain regions and wherein the semiconductor device comprises an NMOS transistor. 
     
     
         11 . The semiconductor device of  claim 1  further comprising a gate insulating layer between the gate electrode and the channel region. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the gate insulating layer comprises a high-k material. 
     
     
         13 . The semiconductor device of  claim 11 , wherein the gate insulating layer further extends along sidewalls of the gate electrode. 
     
     
         14 . The semiconductor device of  claim 1 , wherein the gate electrode comprises a metal material. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the metal material comprises at least one selected from the group consisting of: Al, TiN, TaN, Ti. 
     
     
         16 . The semiconductor device of  claim 1 , wherein the channel region has a lower boundary that lies below lower boundaries of the first and second stress-generating epitaxial regions, relative to an upper surface of the substrate. 
     
     
         17 . The semiconductor device of  claim 1 , wherein the channel region is positioned in a recess in the substrate so that a lower boundary of the channel region lies below lower boundaries of the first and second stress-generating epitaxial regions. 
     
     
         18 . The semiconductor device of  claim 1 , wherein the channel region has an upper surface that is higher than upper surfaces of the first and second stress-generating epitaxial regions. 
     
     
         19 . The semiconductor device of  claim 1 , wherein the substrate extends in a horizontal direction and wherein the first and second stress-generating epitaxial regions are spaced apart from each other in the horizontal direction.