Antifuses and methods of forming antifuses and antifuse structures

Abstract

Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit devices and semiconductor devices. The use of materials having different work function values in the fabrication of recessed access device antifuses allows the breakdown areas of the antifuse device to be customized or predicted.

1 . A method for fabricating at least one antifuse structure, comprising:
 providing a semiconductor substrate having at least one trench formed therein, the at least one trench lined with an oxide material;   forming a first material in the trench, the first material isolated from the semiconductor substrate by the oxide material;   forming a second material in the trench and in contact with the oxide material and the first material in the trench, the second material confined within lateral boundaries of the trench and isolated from the semiconductor substrate by at least one of the oxide material and the first material, a work function value of the second material higher than a work function value of the first material; and   forming a gate over the first material and the second material in the trench.   
     
     
         2 . The method of  claim 1 , wherein providing a semiconductor substrate having at least one trench formed therein comprises providing a semiconductor substrate having at least one trench having an at least partially spherically shaped bottom portion extending beyond the lateral boundaries of an upper portion of the trench. 
     
     
         3 . The method of  claim 1 , further comprising forming a barrier between the first material and the second material in the trench. 
     
     
         4 . The method of  claim 1 , wherein forming the second material within the trench comprises forming the second material within a bottom portion of the trench. 
     
     
         5 . The method of  claim 1 , wherein forming the first material in the trench comprises forming the first material over the second material. 
     
     
         6 . The method of  claim 1 , further comprising forming a barrier over the second material, the first material overlying the barrier. 
     
     
         7 . The method of  claim 1 , wherein forming the first material within the trench comprises forming the first material on at least a portion of surfaces of the trench. 
     
     
         8 . The method of  claim 1 , wherein forming the second material within the trench comprises forming the second material within an opening in the first material. 
     
     
         9 . The method of  claim 1 , further comprising removing at least a portion of the first material within trench to form opening extending through the first material to a bottom of the trench, and wherein forming the second material comprises forming the second material within the opening and to the bottom of the trench. 
     
     
         10 . An antifuse, comprising:
 a recessed access device, comprising:
 a trench in a semiconductor substrate; 
 an oxide material positioned over at least a portion of the trench surface; 
 a material within the trench and contacting at least a portion of the oxide material; 
 a barrier within the trench and overlying the material, the barrier contacting at least an additional portion of the oxide material; 
 another material within the trench and overlying the barrier, the another material contacting at least another portion of the oxide material; and 
 a gate overlying the another material; and 
   a breakdown area in the recessed access device, the breakdown area located at an intersection of the material, the barrier, the another material, and the oxide material.   
     
     
         11 . (canceled) 
     
     
         12 . The antifuse of  claim 10 , wherein the trench in the recessed access device exhibits a substantially spherical bottom portion. 
     
     
         13 . The antifuse of  claim 12 , wherein the substantially spherical bottom portion extends beyond lateral boundaries of an upper portion of the trench. 
     
     
         14 . The antifuse of  claim 13 , wherein the at least an additional portion of the oxide material is located adjacent a portion of the trench where the substantially spherical bottom portion of the trench meets with the upper portion of the trench. 
     
     
         15 . The antifuse of  claim 10 , wherein a work function value of the another material is lower than a work function value of the material. 
     
     
         16 . The antifuse of  claim 10 , wherein the material comprises a p-type doped polysilicon material, and the another material comprises an n-type doped polysilicon material. 
     
     
         17 . The antifuse of  claim 10 , wherein the barrier material is directly on the material and the another material is directly on the barrier material. 
     
     
         18 . The antifuse of  claim 10 , wherein the oxide material is confined within boundaries of the trench. 
     
     
         19 . The antifuse of  claim 10 , further comprising an additional material within the trench and overlying the another material, the additional material contacting at least a further portion of the oxide material. 
     
     
         20 . The antifuse of  claim 19 , further comprising another barrier within the trench and between the another material and the additional material. 
     
     
         21 . A method of forming an antifuse, comprising:
 forming a trench in a semiconductor substrate;   forming an oxide material over at least one surface of the trench;   forming a material over and in contact with the oxide material within a bottom portion of the trench;   forming barrier over the material within the trench, the barrier contacting a portion of the oxide material;   forming another material over the barrier within an upper portion of the trench, the another material contracting another portion of the oxide material; and   forming a gate over the another material.