Segmented guard ring structures with electrically insulated gap structures and design structures thereof

Abstract

Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure.

What is claimed: 
     
         1 . A structure comprising:
 a discontinuous guard ring structure in dielectric layers comprising a plurality of metal layers surrounding an active area of a chip;   a gap in an underlying substrate formed between segments of the discontinuous guard ring structure; and   an electrically insulating structure within the gap to reduce or eliminate device coupling of integrated circuit chips.   
     
     
         2 . The structure of  claim 1 , further comprising diffusion regions to electrically insulate the gap in the underlying substrate formed by segmented portions of the discontinuous guard ring structure. 
     
     
         3 . The structure of  claim 2 , wherein the diffusion regions are formed in a silicon on insulator (SOI) substrate. 
     
     
         4 . The structure of  claim 3 , wherein the diffusion regions are abutting edges of a shallow trench isolation (STI) structure formed in the SOI substrate. 
     
     
         5 . The structure of  claim 4 , wherein the diffusion regions are in direct contact with the plurality of metal layers of the discontinuous guard ring structure. 
     
     
         6 . The structure of  claim 2 , wherein the diffusion regions are in a low resistivity substrate. 
     
     
         7 . The structure of  claim 6 , further comprising an oppositely charged diffusion region between the diffusion regions in the low resistivity substrate. 
     
     
         8 . The structure of  claim 6 , further comprising additional diffusion regions in an upper portion of the low resistivity substrate, wherein the additional diffusion regions are in contact with the diffusion regions in the low resistivity substrate and the plurality of metal layers of the discontinuous guard ring structure. 
     
     
         9 . The structure of  claim 8 , wherein the additional diffusion regions are abutting an STI structure. 
     
     
         10 . The structure of  claim 8 , wherein the additional diffusion regions are directly on p-well diffusion regions. 
     
     
         11 . The structure of  claim 2 , wherein the diffusion regions are in a high resistivity substrate. 
     
     
         12 . The structure of  claim 11 , further comprising a noble implant region in the high resistivity substrate between the diffusion regions. 
     
     
         13 . The structure of  claim 12 , wherein the noble implant region comprises implanted argon into the high resistivity substrate, below an STI structure. 
     
     
         14 . A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a guard ring structure with an electrically insulated gap, wherein the guard ring structure with the electrically insulated gap comprises:
 a discontinuous guard ring structure in dielectric layers comprising a plurality of metal layers surrounding an active area of a chip;   a gap in an underlying substrate formed between segments of the discontinuous guard ring structure; and   an electrically insulating structure within the gap to reduce or eliminate device coupling of integrated circuit chips.