Nanowires and nanowire fielde-effect transistors

Abstract

A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.

1 - 12 . (canceled) 
     
     
         13 . A nanowire field-effect transistor, comprising:
 a first semiconductor substrate;   a buried layer on the first semiconductor substrate;   a nanowire suspended over the buried layer by a through-hole separating the nanowire from a top surface of the buried layer, wherein the nanowire comprises:
 a first nanowire deposited on the buried layer, the first nanowire comprising a first polygon-shaped cross-section having a first number of sides, and 
 a semiconductor layer deposited on all exposed surface of the first nanowire, wherein the semiconductor layer has a second polygon-shaped cross-section containing the first polygon-shaped cross-section of the first nanowire, the second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number of sides, 
 wherein the nanowire is an annealed nanowire from annealing of the semiconductor layer and the first nanowire, to remove a substantial number of vertexes of the second polygon-shaped cross-section of the semiconductor layer, wherein the nanowire has a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section; 
   a gate structure covering the nanowire; and   a source and a drain connecting with the nanowire and both disposed on the buried layer.   
     
     
         14 . The nanowire field-effect transistor according to  claim 13 , wherein:
 the nanowire has a circular cross-section, or an elliptical cross-section, or a “Ω” shape cross-section.   
     
     
         15 . The nanowire field-effect transistor according to  claim 13 , wherein:
 the first semiconductor substrate is silicon,   the nanowire is silicon, and   the buried layer is silicon oxide.   
     
     
         16 . (canceled) 
     
     
         17 . The nanowire field-effect transistor according to  claim 14 , wherein:
 the gate structure comprises a surrounding gate structure surrounding the nanowire with a circular cross-section or an elliptical cross-section, and   the gate structure comprises a gate dielectric layer surrounding the nanowire, and a gate layer covering the gate dielectric layer.   
     
     
         18 . The nanowire field effect transistor according to  claim 14 , wherein:
 a “Ω” shape gate structure surrounds the nanowire with a “Ω” shape cross-section.   
     
     
         19 . The nanowire field-effect transistor according to  claim 17 , wherein:
 the gate layer is made of one or more of tungsten, aluminum, copper, gold, tantalum, vanadium, titanium nitride, zirconium nitride, hafnium nitride, vanadium nitride, niobium nitride, tantalum nitride, tungsten nitride, aluminum titanium nitride, tantalum carbide, tantalum magnesium nitride, and tantalum carbo-nitride.   
     
     
         20 . The nanowire field-effect transistor according to  claim 17 , wherein:
 the gate dielectric layer is a high-K dielectric layer made of one or more of hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, titanium oxide, strontium titanate, barium titanate, lanthanum aluminum oxide, yttrium oxide, hafnium oxynitride, zirconium oxynitride, lanthanum oxynitride, aluminum oxynitride, titanium oxynitride, barium strontium oxynitride, lanthanum aluminum oxynitride and yttrium oxynitride.   
     
     
         21 . The nanowire field-effect transistor according to  claim 13 , wherein:
 the first polygon of the first nanowire is a square or a rectangular; the first number is four; and the first nanowire has a (100) crystal face, a (−100) crystal face, a (010) crystal face, and a (0-10) crystal face.   
     
     
         22 . The nanowire field-effect transistor according to  claim 13 , wherein:
 the second polygon of the semiconductor layer on the first nanowire has a side number greater than five, and the semiconductor layer at least has a (100) crystal face, a (−100) crystal face, a (010) crystal face, a (0-10) crystal face, a (1-10) crystal face, and a (110) crystal face.   
     
     
         23 . The nanowire field-effect transistor according to  claim 13 , wherein:
 the second polygon is octagonal and the semiconductor layer on the first nanowire has a (100) crystal face, a (−100) crystal face, a (010) crystal face, a (0-10) crystal face, a (1-10) crystal face, a (110) crystal face, a (−110) crystal face, and a (−1-10) crystal face.   
     
     
         24 . The nanowire field-effect transistor according to  claim 13 , wherein:
 the source and drain are disposed in parallel on the buried layer, and the first nanowire is connected to each of the source and drain by an extended trapezoid.   
     
     
         25 . The nanowire field-effect transistor according to  claim 13 , wherein:
 the nanowire, the source, and the drain are formed from a second semiconductor substrate, and   each of the first semiconductor substrate, the nanowire, the source region, and the drain region comprises one or more of Si, SiGe, SiC, Ge, and III-V semiconductors.   
     
     
         26 . A nanowire field-effect transistor, comprising:
 a first semiconductor substrate;   a buried layer on the first semiconductor substrate;   a second semiconductor substrate on the buried layer, the second semiconductor substrate comprising a nanowire, a source, and a drain, the nanowire having one end connecting to the source and the other end connecting to the drain on the buried layer,   wherein the nanowire comprises:
 a first nanowire deposited over the buried layer, the first nanowire comprising a first polygon-shaped cross-section having a first number of sides, and 
 a semiconductor layer deposited on all exposed surface of the first nanowire, wherein the semiconductor layer has a second polygon-shaped cross-section containing the first polygon-shaped cross-section of the first nanowire, the second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number of sides, 
 wherein the nanowire is an annealed nanowire from annealing of the semiconductor layer and the first nanowire, to remove a substantial number of vertexes of the second polygon-shaped cross-section of the semiconductor layer, wherein the nanowire has a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section; and 
   a gate structure covering the nanowire.   
     
     
         27 . The nanowire field-effect transistor according to  claim 26 , wherein:
 the first nanowire is disposed on the buried layer and contacting the buried layer.   
     
     
         28 . The nanowire field-effect transistor according to  claim 26 , wherein:
 the nanowire has a circular cross-section, or an elliptical cross-section, or a “Ω” shape cross-section.   
     
     
         29 . The nanowire field effect transistor according to  claim 26 , wherein:
 the gate structure surrounds the nanowire and comprises a “Ω” shape gate structure surrounding on the nanowire with a “Ω” shape cross-section.   
     
     
         30 . The nanowire field-effect transistor according to  claim 26 , wherein:
 the source and the drain are disposed in parallel on the buried layer, and the first nanowire is connected to each of the source and the drain by an extended trapezoid.   
     
     
         31 . The nanowire field-effect transistor according to  claim 26 , wherein:
 each of the first semiconductor substrate and the second semiconductor substrate comprises one or more of Si, SiGe, SiC, Ge, and III-V semiconductors.   
     
     
         32 . The nanowire field-effect transistor according to  claim 26 , wherein:
 the first polygon of the first nanowire is a square or a rectangular; the first number is four; and the first nanowire has a (100) crystal face, a (−100) crystal face, a (010) crystal face, and a (0-10) crystal face, and   the second polygon of the semiconductor layer on the first nanowire has a side number greater than five, and the semiconductor layer at least has a (100) crystal face, a (−100) crystal face, a (010) crystal face, a (0-10) crystal face, a (1-10) crystal face, and a (110) crystal face.   
     
     
         33 . The nanowire field-effect transistor according to  claim 26 , wherein:
 the second polygon is octagonal and the semiconductor layer on the first nanowire has a (100) crystal face, a (−100) crystal face, a (010) crystal face, a (0-10) crystal face, a (1-10) crystal face, a (110) crystal face, a (−110) crystal face, and a (−1-10) crystal face.