Devices Formed With Dual Damascene Process

Abstract

Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

What is claimed is: 
     
         1 . A semiconductor device comprising multiple levels of metallization, at least one metallization level comprising:
 a first metal level overlying a via level, the first metal level comprising metal lines embedded in an insulating layer; and   vias disposed in the via level, and disposed underneath the first metal level, wherein a top width of the metal lines in a region overlying the vias is about the same as a top width of the metal lines in a region not overlying the vias.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the metal lines comprise a first metal line, wherein the vias comprise a first via, and wherein the first metal line and the first via are formed as a single structure without a diffusion layer separating the first via from the first metal line. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the vias and the metal lines comprise copper. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the metal lines comprise a first metal line having first sidewalls, wherein the vias comprise a first via having second sidewalls, and wherein a metal liner continuously covers the first sidewalls and the second sidewalls. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the metal liner comprises a diffusion barrier metal. 
     
     
         6 . The semiconductor device of  claim 4 , wherein the metal liner comprises a material selected from the group consisting of titanium nitride, titanium, tantalum, tantalum nitride, tungsten nitride, tungsten carbo nitride (WCN), and ruthenium. 
     
     
         7 . The semiconductor device of  claim 4 , wherein a conductive material is disposed within the metal liner thereby forming the first via and the first metal line. 
     
     
         8 . The semiconductor device of  claim 1 , wherein a top view of the first via comprises four sides, wherein two of the four sides along a width comprise an arc shape and the remaining two of the four sides along a length are linear, the length being longer than the width, wherein the length and width are measured along a surface parallel to a top surface of the insulating layer. 
     
     
         9 . An interconnect structure comprising:
 a first metal line disposed in a first insulating layer;   a second insulating layer disposed on the first insulating layer;   a first via disposed in the second insulating layer, the first via disposed on the first metal line; and   a second metal line disposed in the second insulating layer, wherein at least a portion of the second metal line is disposed on the first via, and wherein a bottom critical dimension (CD) of the second metal line in a region overlying the first via is about the same as a top CD of the first via.   
     
     
         10 . The interconnect structure of  claim 9 , wherein the second metal line and the first via are formed as a single structure without a diffusion layer separating the first via from the second metal line. 
     
     
         11 . The interconnect structure of  claim 9 , wherein the second metal line has first sidewalls, wherein the first via has second sidewalls, and wherein a metal liner continuously covers the first sidewalls and the second sidewalls. 
     
     
         12 . The interconnect structure of  claim 11 , wherein the metal liner comprises a diffusion barrier metal. 
     
     
         13 . The interconnect structure of  claim 11 , wherein the metal liner comprises a material selected from the group consisting of titanium nitride, titanium, tantalum, tantalum nitride, tungsten nitride, tungsten carbo nitride (WCN), and ruthenium. 
     
     
         14 . The interconnect structure of  claim 11 , wherein a conductive material is disposed within the metal liner thereby forming the first via and the second metal line. 
     
     
         15 . The interconnect structure of  claim 14 , wherein the conductive material comprises copper. 
     
     
         16 . The interconnect structure of  claim 14 , wherein the conductive material comprises a material selected from the group consisting of gold and tungsten. 
     
     
         17 . The interconnect structure of  claim 9 , wherein a top view of the first via comprises four sides, wherein two of the four sides comprise an arc shape and the remaining two of the four sides are linear, wherein the bottom critical dimension (CD) is measured at the bottom of the second metal line and measures a distance between the two linear sides. 
     
     
         18 . The interconnect structure of  claim 17 , further comprising:
 a third metal line disposed in the first insulating layer; and   a second via disposed in the second insulating layer, the second via disposed on the third metal line; and   a fourth metal line disposed in the second insulating layer.   
     
     
         19 . The interconnect structure of  claim 18 , wherein at least a portion of the fourth metal line is disposed on the second via, and wherein a bottom critical dimension (CD) of the fourth metal line in a region overlying the second via is about the same as a top CD of the second via, wherein the bottom CD is measured at the bottom of the fourth metal line and measures a distance between the two linear sides. 
     
     
         20 . The interconnect structure of  claim 18 , wherein a top view of the second via comprises four sides, wherein two of the four sides of the second via comprise an arc shape and the remaining two of the four sides are linear. 
     
     
         21 . An interconnect structure comprising:
 a first metal line disposed in a first insulating layer;   a second insulating layer disposed on the first insulating layer;   a first via disposed in the second insulating layer, the first via disposed on the first metal line; and   a second metal line disposed in the second insulating layer, wherein at least a portion of the second metal line is disposed on the first via, and wherein a top view of the first via comprises four sides, wherein two of the four sides comprise an arc shape along a width of the second metal line and the remaining two of the four sides along a length of the second metal line are linear, the length being longer than the width, wherein the length and width are measured along a surface parallel to a top surface of the first insulating layer.   
     
     
         22 . The interconnect structure of  claim 21 , wherein the second metal line and the first via are formed as a single structure without a diffusion layer separating the first via from the second metal line. 
     
     
         23 . The interconnect structure of  claim 21 , further comprising:
 a third metal line disposed in the first insulating layer; and   a second via disposed in the second insulating layer, the second via disposed on the third metal line; and   a fourth metal line disposed in the second insulating layer, wherein a top view of the second via comprises four sides, wherein two of the four sides of the second via along a width of the second via comprise an arc shape and the remaining two of the four sides of the second via along a length of the fourth metal line are linear.   
     
     
         24 . The interconnect structure of  claim 23 , wherein the second metal line has first sidewalls, wherein the first via has second sidewalls, and wherein a first metal liner continuously covers the first sidewalls and the second sidewalls. 
     
     
         25 . The interconnect structure of  claim 24 , wherein the fourth metal line has third sidewalls, wherein the second via has fourth sidewalls, and wherein a second metal liner continuously covers the third sidewalls and the fourth sidewalls.