Continuously scalable width and height semiconductor fins

Abstract

Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a first semiconductor fin having a first height and a first width and located on an insulator layer;   a second semiconductor fin having said first height and a second width that is less than said first width and located on said insulator layer; and   a vertical stack of a third semiconductor fin and a dielectric cap portion located on said insulator layer, said third semiconductor fin having a second height that is less than said first height.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein said vertical stack has said first width. 
     
     
         3 . The semiconductor structure of  claim 2 , further comprising another vertical stack of a fourth semiconductor fin and another dielectric cap portion located on said insulator layer. 
     
     
         4 . The semiconductor structure of  claim 3 , wherein said another vertical stack has said second width and said fourth semiconductor fin has said second height. 
     
     
         5 . The semiconductor structure of  claim 1 , further comprising:
 a first field effect transistor comprising a first source region, a first drain region, and a first body region that are located within said first semiconductor fin;   a second field effect transistor comprising a second source region, a second drain region, and a second body region that are located within said second semiconductor fin; and   a third field effect transistor comprising a third source region, a third drain region, and a third body region that are located within said third semiconductor fin.   
     
     
         6 . The semiconductor structure of  claim 1 , further comprising:
 another dielectric cap portion in contact with a top surface of said first semiconductor fin; and   yet another dielectric cap portion in contact with a top surface of said second semiconductor fin.   
     
     
         7 . The semiconductor structure of  claim 6 , wherein a topmost surface of said dielectric cap portion is coplanar with a topmost surface of said another dielectric cap portion and a topmost surface of said yet another dielectric cap portion. 
     
     
         8 . The semiconductor structure of  claim 6 , further comprising:
 a first spacer structure in contact with said topmost surface of said another dielectric cap portion and having said first width; and   a second spacer structure in contact with said topmost surface of said yet another dielectric cap portion and having said second width.   
     
     
         9 . The semiconductor structure of  claim 8 , wherein said first spacer structure comprises a dielectric material and said second spacer structure comprises said dielectric material and at least one dopant material, wherein said at least one dopant material is not present within said first spacer structure. 
     
     
         10 . The semiconductor structure of  claim 9 , wherein said at least one dopant material includes at least one of P, As, Sb, B, Ar, Xe, Ge, Si, and C. 
     
     
         11 . The semiconductor structure of  claim 8 , wherein a difference between a first height of said first spacer structure and a second height of said second spacer structure is the same as a difference between said first width and said second width.