Integrated circuit for detecting defects of through chip via

Abstract

An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.

1 - 8 . (canceled) 
     
     
         9 . An integrated circuit comprising:
 a semiconductor substrate configured to include a first well region and a second well region, the first well region being doped by a first impurity, and the second well region being doped by a second impurity different from the first impurity;   a plurality of through silicon vias formed in the first well region;   an output pad selectively coupled to each of the through silicon vias;   current forming unit configured to form a current between the semiconductor substrate and the plurality of through silicon vias; and   a current path providing unit configured to provide a current, flowing between the semiconductor substrate and a selected one of the plurality of through silicon vias, to the output pad during a test mode.   
     
     
         10 . The integrated circuit of  claim 9 , wherein the current path providing unit comprises;
 a switching controller, formed in the second well region, configured to generate a plurality of switching control signals in response to a test mode signal, and   a plurality of switching units, formed in the second well region, configured to sequentially connect the plurality of through silicon vias to the output pad in response to the plurality of switching control signals.   
     
     
         11 . The integrated circuit of  claim 10 , wherein the current path providing unit further comprises a plurality of input/output units electrically coupled to the through silicon vias, respectively, the input/output units each configured to be enabled in a normal mode and disabled in the test mode. 
     
     
         12 . The integrated circuit of  claim 9 , further comprising:
 a first well biasing region, formed in the first well region, configured to receive a first voltage; and   a second well biasing region, formed in the second well region, configured to receive a second voltage different from the first voltage to electrically separate the first well region and the second well region during a test mode.   
     
     
         13 . The integrated circuit of  claim 12 , wherein the first voltage is greater than a potential barrier between the semiconductor substrate and the selected through silicon via, during the test mode. 
     
     
         14 . The integrated circuit of  claim 13 , wherein the first voltage is a ground voltage, during a normal mode. 
     
     
         15 . The integrated circuit of  claim 14 , wherein the second voltage is the ground voltage. 
     
     
         16 . The integrated circuit of  claim 9 , further comprising a plurality of isolation layers, each configured to surround sidewalls of a corresponding one of the plurality of through silicon vias to isolate the corresponding through silicon via from the semiconductor substrate. 
     
     
         17 . The integrated circuit of  claim 9 , wherein each of the plurality of through silicon vias comprises a through silicon via (TSV). 
     
     
         18 . (canceled) 
     
     
         19 . The integrated circuit of  claim 9 , wherein the current forming unit forms the current between the semiconductor substrate and the plurality of through silicon via in response to a bias voltage being greater than a potential barrier between the semiconductor substrate and the plurality of through silicon via, during the test mode. 
     
     
         20 . The integrated circuit of  claim 19 , wherein the current forming unit comprises a schottky diode electrically connected between the semiconductor substrate and the plurality of through silicon via. 
     
     
         21 . The integrated circuit of  claim 20 , wherein the plurality of through silicon via and the schottky diode are formed in a first region of the semiconductor substrate, and
 the current providing unit is formed in a second region of the semiconductor substrate, the second region being doped by a second impurity different from a first impurity doping the first region and being electrically separated from the first region, during the test mode.   
     
     
         22 . The integrated circuit of  claim 21 , wherein the first region comprises a P-type well, and the second region comprises an N-type well. 
     
     
         23 . The integrated circuit of  claim 22 , wherein the second region of the semiconductor substrate receives a ground voltage, during the test mode. 
     
     
         24 . The integrated circuit of  claim 19 , wherein the current path providing unit comprises a switching unit, electrically connected between the plurality of through silicon via and the output pad, configured to allow current to pass in response to a control signal indicating the test mode. 
     
     
         25 . The integrated circuit of  claim 24 , wherein the current path providing unit further comprises an input/output unit electrically coupled to the plurality of through silicon via, the input/output unit configured to be enabled in a normal mode and disabled in the test mode. 
     
     
         26 . The integrated circuit of  claim 9 , wherein a first voltage is applied to a first well region of the semiconductor substrate during the test mode, the first voltage being greater than a schottky potential barrier formed at contact interface between a bottom of the plurality of silicon vias and the semiconductor substrate.