Landing structure for through-silicon via

Abstract

Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In one embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.

What is claimed is: 
     
         1 . An apparatus comprising:
 a semiconductor substrate having a first surface and a second surface opposite to the first surface;   a through-silicon via (TSV) disposed between the first surface and the second surface; and   a landing structure of the TSV, the landing structure including trench structures and via structures.   
     
     
         2 . The apparatus of  claim 1 , wherein:
 the trench structures are arranged in a grid pattern having regions between the trench structures; and   the via structures are at least partially disposed in the regions between the trench structures.   
     
     
         3 . The apparatus of  claim 1 , wherein:
 the trench structures are trench structures of a trench layer that are disposed at an interface of the TSV; and   the via structures are via structures of a via layer that are disposed at the interface, the via layer being disposed on the trench layer.   
     
     
         4 . The apparatus of  claim 3 , wherein the trench structures are first trench structures, the trench layer is a first trench layer, and the landing structure further comprises:
 second trench structures of a second trench layer that are disposed directly on the via structures of the via layer.   
     
     
         5 . The apparatus of  claim 1 , wherein:
 a width of the trench structures is from 50 nanometers (nm) to 150 nm; and   a width of the TSV is greater than 1000 nm.   
     
     
         6 . The apparatus of  claim 1 , further comprising:
 a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices; and   interconnect layers disposed on the device layer, the interconnect layers including the trench structures and the via structures.   
     
     
         7 . The apparatus of  claim 6 , wherein the trench structures are part of a trench layer that is positioned closest to the device layer relative to other trench layers of the interconnect layers. 
     
     
         8 . The apparatus of  claim 6 , wherein the device layer includes one or more dummy transistor devices disposed between the one or more transistor devices and the TSV. 
     
     
         9 . The apparatus of  claim 1 , wherein:
 the trench structures and the via structures comprise copper (Cu);   the TSV comprises Cu; and   the semiconductor substrate comprises silicon (Si).   
     
     
         10 . A method comprising:
 providing a semiconductor substrate having a first surface and a second surface opposite to the first surface;   forming a through-silicon via (TSV) between the first surface and the second surface; and   forming a landing structure of the TSV, the landing structure including trench structures and via structures.   
     
     
         11 . The method of  claim 10 , wherein:
 forming the landing structures comprises forming the trench structures such that the trench structures arranged in a grid pattern having regions between the trench structures; and   forming the landing structures comprise forming the via structures such that the via structures are at least partially disposed in the regions between the trench structures.   
     
     
         12 . The method of  claim 10 , wherein:
 the trench structures are trench structures of a trench layer that are disposed at an interface of the TSV; and   the via structures are via structures of a via layer that are disposed at the interface, the via layer being disposed on the trench layer.   
     
     
         13 . The method of  claim 12 , wherein the trench structures are first trench structures, the trench layer is a first trench layer, and forming the landing structure further comprises:
 forming second trench structures of a second trench layer that are disposed directly on the via structures of the via layer.   
     
     
         14 . The method of  claim 10 , wherein:
 a width of the trench structures is from 50 nanometers (nm) to 150 nm; and   a width of the TSV is greater than 1000 nm.   
     
     
         15 . The method of  claim 10 , further comprising:
 forming a device layer on the first surface of the semiconductor substrate, the device layer including one or more transistor devices; and   forming interconnect layers on the device layer, the interconnect layers including the trench structures and the via structures.   
     
     
         16 . The method of  claim 15 , wherein the trench structures are part of a trench layer that is positioned closest to the device layer relative to other trench layers of the interconnect layers. 
     
     
         17 . The method of  claim 15 , wherein the device layer includes one or more dummy transistor devices disposed between the one or more transistor devices and the TSV. 
     
     
         18 . A system comprising:
 a circuit board; and   a die coupled with the circuit board, the die including:
 a semiconductor substrate having a first surface and a second surface opposite to the first surface; 
 a through-silicon via (TSV) disposed between the first surface and the second surface; and 
 a landing structure of the TSV, the landing structure including trench structures and via structures. 
   
     
     
         19 . The system of  claim 18 , wherein the die is a motherboard. 
     
     
         20 . The system of  claim 18 , wherein the system is one of a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder, the system further comprising one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, or a mass storage device operatively coupled with circuit board.