Semiconductor device

Abstract

A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate including a chip region;   a plurality of dielectric films formed over the substrate;   seal rings formed in a peripheral part of a chip region, the seal rings including a first seal ring and a second seal ring, the first seal ring surrounding the second seal ring, the first seal ring and the second seal ring both provided through at least one of the plurality of dielectric films in the peripheral part of the chip region;   an interconnect formed in the plurality of dielectric films in the chip region;   a first dielectric film included in the plurality of dielectric films and being in contact with an upper surface of the interconnect;   a first opening provided in the first dielectric film and on the first seal ring;   a second opening provided in the first dielectric film and on the second seal ring;   a third opening provided in the first dielectric film and on the interconnect;   a first cap layer disposed in the first opening and in contact with the first seal ring;   a second cap layer disposed in the second opening and in contact with the second seal ring; and   a pad electrode disposed in the third opening and in contact with the interconnect,   wherein the plurality of dielectric films includes a second dielectric film and a third dielectric film, both of the second and third dielectric films between the substrate and the first dielectric film,   at least one of the first and second seal rings includes one or more first seal vias in the second dielectric film and one or more second seal vias in the third dielectric film,   the second dielectric film is between the substrate and the third dielectric film, and   a height of one of the second seal vias is larger than a height of one of the first seal vias.   
     
     
         2 . The semiconductor device of  claim 1 , wherein a thickness of a center of the first cap layer in a depth direction is larger than a thickness of the first dielectric film in the depth direction. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a distance between an edge of the first cap layer located farther from the second seal ring and a point on the second seal ring contacting the second cap layer is greater than a distance between an edge of the first seal ring located farther from the second seal ring and the point on the second seal ring. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a width of the first cap layer is larger than a width of the first opening. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a width of the second cap layer is larger than a width of the second opening. 
     
     
         6 . The semiconductor device of  claim 1 , wherein a distance from an interface between the first cap layer and the first seal ring to the substrate is substantially equal to a distance from the upper surface of the interconnect to the substrate. 
     
     
         7 . The semiconductor device of  claim 1 , wherein
 the plurality of dielectric films includes a fourth dielectric film between the substrate and the first dielectric film and in contact with the first dielectric film, and   a width of the first cap layer is larger than a width of the first seal ring formed in the fourth dielectric film.   
     
     
         8 . The semiconductor device of  claim 1 , wherein at least one of the first and second seal rings includes two or more seal vias in a same layer. 
     
     
         9 . The semiconductor device of  claim 1 , wherein
 a width of one of the second seal vias is larger than a width of one of the first seal vias.   
     
     
         10 . The semiconductor device of  claim 1 , wherein the first seal ring is an outermost seal ring of the seal rings. 
     
     
         11 . The semiconductor device of  claim 1 , wherein
 the interconnect is one of a plurality of interconnects formed in the plurality of dielectric films in the chip region, and   the interconnect is the closest of the plurality of interconnects to the first dielectric film.   
     
     
         12 . The semiconductor device of  claim 1 , wherein the first dielectric film includes silicon and nitrogen. 
     
     
         13 . The semiconductor device of  claim 1 , wherein the first cap layer is an outermost cap layer of cap layers formed on the first dielectric film. 
     
     
         14 . The semiconductor device of  claim 1 , wherein the one or more second seal vias are the closest of a plurality of seal vias to the first dielectric film, and
 at least one of the first and second seal rings includes only two second seal vias when a width is viewed in a cross-section taken in a thickness direction of the semiconductor device.   
     
     
         15 . The semiconductor device of  claim 14 , wherein the at least one of the first and second seal rings includes two or more seal vias directly below at least one of the only two second seal vias.