Semiconductor structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a substrate;   at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and   a shallow trench isolation (STI) made of an insulating layer disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the fin group includes a plurality of main fin structures. 
     
     
         3 . The semiconductor structure of  claim 2 , further comprising a liner, covering each sub-fin structure entirely and parts of each fin structure. 
     
     
         4 . The semiconductor structure of  claim 3 , wherein each main fin structure comprises at least two edges exposed by the liner. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the height from a top surface of the insulating layer to a top surface of the fin group is labeled as “X”, and the height from a bottom of the insulating layer to a top surface of the sub-fin structure is between 0.9X˜2X. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein a top surface of the shallow trench isolation is lower than the top surface of the fin group. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein a top surface of the shallow trench isolation is higher than the top surface of the sub-fin structure. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein each sub-fin structure is a floating structure. 
     
     
         9 . A manufacturing method for forming a semiconductor structure, comprising the following steps:
 providing a substrate, having a plurality of dummy fin structures being disposed on the substrate, and a plurality of patterned hard masks being disposed on the dummy fin structures;   removing parts of the patterned hard masks disposed on the dummy fin structures;   performing an etching process, so as to form at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein a top surface of each sub-fin structure is lower than a top surface of the fin group; and   forming a shallow trench isolation made of an insulating layer in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.   
     
     
         10 . The method of  claim 9 , wherein the process for removing parts of the patterned hard masks comprises:
 forming a patterned photoresist layer to cover parts of the dummy fin structures and parts of the patterned hard masks; and   performing an etching process, to remove the patterned hard masks that are not covered by the patterned photoresist layer.   
     
     
         11 . The method of  claim 9 , further comprising performing a planarization process after the insulating layer is formed on the fin group and one of the sub-fin structures. 
     
     
         12 . The method of  claim 11 , further comprising performing an etching back process to the insulating layer, so as to expose parts of the fin group. 
     
     
         13 . The method of  claim 11 , further comprising performing an anneal process to the insulating layer. 
     
     
         14 . The method of  claim 9 , wherein the fin group is disposed between two sub-fin structures. 
     
     
         15 . The method of  claim 9 , wherein each sub-fin structure is a floating structure. 
     
     
         16 . The method of  claim 9 , wherein the fin group includes a plurality of main fin structures. 
     
     
         17 . The method of  claim 9 , wherein the method for forming the patterned hard mask comprises a sidewall image transfer process.