Stacked semiconductor packages, methods for fabricating the same, and /or systems employing the same

Abstract

An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

1 . (canceled) 
     
     
         2 . An apparatus, comprising:
 a first substrate including a first land;   a second substrate including a second land;   a first semiconductor chip on the first substrate;   a first molding compound between the first substrate and the second substrate, the first molding compound surrounding side surfaces of the first semiconductor chip;   a first connector on the first land; and   a second connector between the second land and the first connector,   a maximum width of the second connector being greater than a maximum width of the first connector, and   the first connector being completely surrounded by the first molding compound.   
     
     
         3 . The apparatus according to  claim 2 , wherein most of the second connector is surrounded by the first molding compound. 
     
     
         4 . The apparatus according to  claim 3 , wherein more than a half of total vertical height of the second connector is surrounded by the first molding compound. 
     
     
         5 . The apparatus according to  claim 3 , wherein an uppermost portion of the second connector protrudes from a top surface of the first molding compound. 
     
     
         6 . The apparatus according to  claim 2 , wherein a top surface of the first molding compound is coplanar with a top surface of the first semiconductor chip. 
     
     
         7 . The apparatus according to  claim 6 , further comprising:
 a space between a bottom surface of the second substrate and the top surfaces of the first semiconductor chip and the first molding compound.   
     
     
         8 . The apparatus according to  claim 2 , wherein a volume of the second connector is greater than a volume of the first connector. 
     
     
         9 . The apparatus according to  claim 2 , wherein a top surface of the first semiconductor chip is higher than an interface between the first connector and the second connector. 
     
     
         10 . The apparatus according to  claim 2 , further comprising:
 a third connector between the first connector and the second connector.   
     
     
         11 . The apparatus according to  claim 10 , wherein the third connector is completely surrounded by the first molding compound. 
     
     
         12 . The apparatus according to  claim 11 , wherein an interface between the third connector and the second connector is lower than a top surface of the first semiconductor chip. 
     
     
         13 . An apparatus, comprising:
 a lower substrate;   an upper substrate;   a lower land on a top surface of the lower substrate;   an upper land on a bottom surface of the upper substrate;   a semiconductor chip on the top surface of the lower substrate;   a lower molding compound between the top surface of the lower substrate and the bottom surface of the upper substrate;   a lower connector on the lower land; and   an upper connector on the upper land,   the lower connector being completely surrounded by the lower molding compound,   most of the upper connector being surrounded by the lower molding compound,   a maximum width of the upper connector being greater than a maximum width of the lower connector, and   a top surface of the lower molding compound being apart from the bottom surface of the upper substrate.   
     
     
         14 . The apparatus according to  claim 13 , further comprising:
 a through silicon via, the through silicon via vertically extending through the semiconductor chip.   
     
     
         15 . The apparatus according to  claim 14 , further comprising:
 a chip connector on the semiconductor chip, the chip connector being electrically connected to the through silicon via.   
     
     
         16 . The apparatus according to  claim 15 , wherein a lower portion of the chip connector is surrounded by the lower molding compound. 
     
     
         17 . An apparatus, comprising:
 a first substrate including a first land;   a second substrate including a second land;   a first semiconductor chip on a top surface of the first substrate;   an second semiconductor chip on a top surface of the second substrate;   a first molding compound between the top surface of the first substrate and a bottom surface of the second substrate, the first molding compound covering side surfaces of the first semiconductor;   a second molding compound on the top surface of the second substrate, the second molding compound covering a top and side surfaces of the second semiconductor;   a first connector contacting the first land; and   a second connector contacting the second land,   the first connector being completely surrounded by the first molding compound,   more than half of vertical thickness of the second connector being surrounded by the first molding compound,   a volume of the second connector being greater than a volume of the first connector, and   top surfaces of the first semiconductor chip and the first molding compound being exposed.   
     
     
         18 . The apparatus according to  claim 17 , wherein the second connector includes at least one of a mesa shaped metal, a stud shaped metal, and a pillar shaped metal. 
     
     
         19 . The apparatus according to  claim 17 , further comprising:
 a flip chip landing pad between the first semiconductor chip and the top surface of the first substrate; and   a chip bump between the flip chip landing pad and the first semiconductor chip.   
     
     
         20 . The apparatus according to  claim 17 , further comprising:
 a wire pad on the top surface of the second substrate, the wire pad being electrically connected to the second land; and   a bonding wire electrically connecting the second semiconductor chip and the wire pad.   
     
     
         21 . The apparatus according to  claim 17 , further comprising:
 a solder ball on a bottom surface of the first substrate.