REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED CHANNEL

Abstract

An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively.

What is claimed is: 
     
         1 . A device comprising:
 a substrate;   a trench in the substrate;   a first gate oxide at a first thickness lining the trench;   a second gate oxide at a second thickness over a portion of the substrate;   a high-k dielectric layer on the first and second gate oxides;   a first replacement metal gate having a first portion filling the trench and a second portion overlying the first portion;   a second replacement metal gate over the second gate oxide; and   first spacers on opposite sides of the second portion of the first replacement metal gate and second spacers on opposite sides of the second replacement metal gate,   wherein the first thickness differs from the second thickness.   
     
     
         2 . The device according to  claim 1 , wherein a width of the second portion of the first replacement metal gate is less than a width of the trench. 
     
     
         3 . The device according to  claim 2 , wherein the width of the second portion of the first replacement metal gate is 5 nm to 20 nm less than the width of the trench. 
     
     
         4 . The device according to  claim 1 , further comprising:
 a third gate oxide at a third thickness over a second portion of the substrate;   a high-k dielectric layer on the third gate oxide;   a third replacement metal gate over the third gate oxide;   third spacers on opposite sides of the third replacement metal gate,   wherein the first thickness is less than the second thickness but greater than the third thickness.   
     
     
         5 . The device according to  claim 4 , wherein:
 the first gate oxide has a thickness of 1 nm to 2 nm;   the second gate oxide has a thickness of 2 nm to 4 nm; and   the third gate oxide has a thickness of 0.5 nm to 1 nm.   
     
     
         6 . The device according to  claim 4 , wherein the second portion of the first replacement metal gate, the second replacement metal gate, and the third replacement metal gate are each formed to a height of 40 nm to 80 nm. 
     
     
         7 . The device according to  claim 4 , further comprising:
 source/drain extensions and source/drain implant regions in the substrate on opposite sides of each of the first, second, and third replacement metal gates.   
     
     
         8 . The device according to  claim 7 , further comprising:
 a silicide over the source/drain implant regions.   
     
     
         9 . The device according to  claim 8 , further comprising an interlayer dielectric (ILD) over the silicide and the substrate, having an upper surface substantially coplanar with an upper surface of the first, second, and third replacement metal gates. 
     
     
         10 . A device comprising:
 a substrate;   a first transistor and a second transistor formed on the substrate, wherein:   the first transistor comprises:
 a u-shaped trench in the substrate, 
 a first gate oxide at a first thickness lining the u-shaped trench, 
 a first high-k dielectric layer on the first gate oxide, 
 a first replacement metal gate having a first portion filling the trench and a second portion overlying the first portion and having a first height, and 
 first spacers on opposite sides of the second portion of the first replacement metal gate; and 
   the second transistor comprises:
 a second gate oxide at a second thickness, greater than the first thickness, over a portion of the substrate, 
 a second high-k dielectric layer on the second gate oxide, 
 a second replacement metal gate over the second high-k dielectric layer and having a second height, and 
 second spacers on opposite sides of the second replacement metal gate, 
   wherein the first and second heights are the same.   
     
     
         11 . The device according to  claim 10 , wherein a width of the second portion of the first replacement metal gate is less than a width of the trench. 
     
     
         12 . The device according to  claim 11 , wherein the width of the second portion of the first replacement metal gate is 5 nm to 20 nm less than the width of the trench. 
     
     
         13 . The device according to  claim 10 , further comprising:
 a third transistor on the substrate, the third transistor comprising:
 a third gate oxide at a third thickness, less than the first thickness, over a second portion of the substrate, 
 a third high-k dielectric layer on the third gate oxide, 
 a third replacement metal gate over the third high-k dielectric layer and having a third height, and 
 third spacers on opposite sides of the third replacement metal gate, 
   wherein the third height is the same as the first height.   
     
     
         14 . The device according to  claim 13 , wherein:
 the first gate oxide has a thickness of 1 nm to 2 nm;   the second gate oxide has a thickness of 2 nm to 4 nm; and   the third gate oxide has a thickness of 0.5 nm to 1 nm.   
     
     
         15 . The device according to  claim 13 , wherein the first, second, and third heights are each 40 nm to 80 nm. 
     
     
         16 . The device according to  claim 13 , further comprising:
 source/drain extensions and source/drain implant regions in the substrate on opposite sides of each of the first, second, and third replacement metal gates.   
     
     
         17 . The device according to  claim 16 , further comprising:
 a silicide over the source/drain implant regions.   
     
     
         18 . The device according to  claim 17 , further comprising an interlayer dielectric (ILD) over the silicide and the substrate, having an upper surface substantially coplanar with an upper surface of the first, second, and third replacement metal gates. 
     
     
         19 . A device comprising:
 a substrate;   a dynamic random-access memory (DRAM) transistor, an access transistor and a logic transistor formed on the substrate, wherein:   the DRAM transistor comprises:
 a u-shaped trench in the substrate, 
 a first gate oxide having a thickness of 1 nm to 2 nm lining the u-shaped trench, 
 a first high-k dielectric layer on the first gate oxide, 
 a first replacement metal gate having a first portion filling the trench and a second portion overlying the first portion, and 
 first spacers on opposite sides of the second portion of the first replacement metal gate; 
   the access transistor comprises:
 a second gate oxide at a thickness of 2 nm to 4 nm over a first portion of the substrate, 
 a second high-k dielectric layer on the second gate oxide, 
 a second replacement metal gate over the second high-k dielectric layer, and 
 second spacers on opposite sides of the second replacement metal gate; and 
   the logic transistor comprises:
 a third gate oxide having a thickness of 0.5 nm to 1 nm over a second portion of the substrate, 
 a third high-k dielectric layer on the third gate oxide, 
 a third replacement metal gate over the third high-k dielectric layer, and 
 third spacers on opposite sides of the third replacement metal gate. 
   
     
     
         20 . The device according to  claim 19 , wherein the second portion of the first replacement metal gate, and the second and third replacement metal gates have first, second, and third heights, respectively, of 40 nm to 80 nm, wherein the first, second, and third heights are the same.