Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.

1 . A semiconductor device, comprising:
 a chip mounting portion;   a semiconductor chip mounted over the chip mounting portion, the semiconductor chip including a plurality of pads;   a plurality of leads;   a plurality of wires electrically connecting the plurality of pads with the plurality of leads, respectively; and   a resin sealing body sealing the semiconductor chip and the plurality of wires, wherein   the plurality of leads include:
 a first lead, and 
 a second lead, 
   the plurality of wires include:
 a first wire electrically connected with the first lead, 
 a second wire electrically connected with the second lead, and 
 a third wire electrically connected with the second lead, 
   a diameter of each of the second and third wires is larger than a diameter of the first wire, and   the number of wires electrically connected with the second lead is greater than the number of wires electrically connected with the first lead.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein
 the first wire is a wire for signal, and   each of the second and third wires is a wire for GND.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein the first wire is only electrically connected with the first lead. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the first lead is connected with the chip mounting portion. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein
 the plurality of pads include a first pad, a second pad and a third pad,   the first, second and third pads are arranged along a first side of the semiconductor chip in plan view,   the third pad is arranged next to the second pad,   the first pad is electrically connected with the first lead via the first wire,   the second pad is electrically connected with the second lead via the second wire, and   the third pad is electrically connected with the second lead via the third wire.   
     
     
         6 . The semiconductor device according to  claim 1 , wherein
 the plurality of pads include a first pad, a second pad and a third pad,   the first, second and third pads are arranged along a first side of the semiconductor chip in plan view,   another pad is not located between the second pad and the third pad,   the first pad is electrically connected with the first lead via the first wire,   the second pad is electrically connected with the second lead via the second wire, and   the third pad is electrically connected with the second lead via the third wire.   
     
     
         7 - 12 . (canceled) 
     
     
         13 . A semiconductor device, comprising:
 a chip mounting portion;   a semiconductor chip mounted over the chip mounting portion, the semiconductor chip including a plurality of pads;   a plurality of leads;   a plurality of wires electrically connecting the plurality of pads with the plurality of leads, respectively; and   a resin sealing body sealing the semiconductor chip and the plurality of wires, wherein   the plurality of leads include:
 a first lead, and 
 a second lead, 
   the plurality of wires include:
 a first wire, 
 a second wire, and 
 a third wire, 
   a diameter of each of the second and third wires is larger than a diameter of the first wire, the first wire is electrically connected with the first lead, and   the second and third wires are electrically connected with the second lead.   
     
     
         14 . The semiconductor device according to  claim 13 , wherein
 the first wire is a wire for signal, and   each of the second and third wires is a wire for GND.   
     
     
         15 . The semiconductor device according to  claim 14 , wherein the first wire is only electrically connected with the first lead. 
     
     
         16 . The semiconductor device according to  claim 14 , wherein the first lead is connected with the chip mounting portion. 
     
     
         17 . The semiconductor device according to  claim 16 , wherein
 the plurality of pads include a first pad, a second pad and a third pad,   the first, second and third pads are arranged along a first side of the semiconductor chip in plan view,   the third pad is arranged next to the second pad,   the first pad is electrically connected with the first lead via the first wire,   the second pad is electrically connected with the second lead via the second wire, and   the third pad is electrically connected with the second lead via the third wire.   
     
     
         18 . The semiconductor device according to  claim 16 , wherein
 the plurality of pads include a first pad, a second pad and a third pad,   the first, second and third pads are arranged along a first side of the semiconductor chip in plan view,   another pad is not located between the second pad and the third pad,   the first pad is electrically connected with the first lead via the first wire,   the second pad is electrically connected with the second lead via the second wire, and   the third pad is electrically connected with the second lead via the third