Cap layers for semiconductor devices with self-aligned contact elements

Abstract

One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes an etch stop layer that is positioned above a recessed replacement gate structure and recessed sidewall spacers, wherein the etch stop layer defines an etch stop recess that contains a layer of insulating material positioned therein. The device further includes a self-aligned contact.

1 .- 19 . (canceled) 
     
     
         20 . A transistor device, comprising:
 a replacement gate structure positioned above a semiconductor substrate, said replacement gate structure having an upper surface;   a sidewall spacers positioned adjacent said replacement gate structure, said sidewall spacer having an upper surface;   a first layer of insulating material positioned above said substrate adjacent said sidewall spacer, said first layer of insulating material having an upper surface;   an etch stop layer positioned above said upper surfaces of said sidewall spacer and said replacement gate structure, wherein said etch stop layer defines an etch stop recess;   a second layer of insulating material positioned within said etch stop recess, said second layer of insulating material having an upper surface that is substantially planar with said upper surface of said first layer of insulating material;   a third layer of insulating material positioned above said first layer of insulating material, said second layer of insulating material and said etch stop layer; and   a conductive contact positioned in an opening formed in at least said third layer of insulating material and said first layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor.   
     
     
         21 . The device of  claim 20 , further comprising a fourth layer of insulating material positioned between said upper surface of said replacement gate structure and said etch stop layer. 
     
     
         22 . The device of  claim 20 , wherein an upper surface of said fourth layer of insulating material is positioned level with or below said upper surface of said sidewall spacer. 
     
     
         23 . The device of  claim 20 , wherein said etch stop layer is comprised of a high-k insulating material. 
     
     
         24 . A transistor device, comprising:
 a replacement gate structure positioned above a semiconductor substrate, said replacement gate structure having an upper surface;   a sidewall spacer positioned adjacent said replacement gate structure, said sidewall spacer having an upper surface that is positioned at a level that is above a level of said upper surface of said replacement gate structure;   a first layer of insulating material positioned above said substrate adjacent said sidewall spacer, said first layer of insulating material having an upper surface;   a second layer of insulating material positioned on said upper surface of said replacement gate structure, said second layer of insulating material having an upper surface;   an etch stop layer positioned on said upper surfaces of said sidewall spacer and on said upper surface of said second layer of insulating material, wherein said etch stop layer defines an etch stop recess;   a third layer of insulating material positioned within said etch stop recess, said third layer of insulating material having an upper surface that is substantially planar with said upper surface of said first layer of insulating material;   a fourth layer of insulating material positioned above said first layer of insulating material, said third layer of insulating material and said etch stop layer; and   a conductive contact positioned in an opening formed in at least said fourth layer of insulating material and said first layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor.   
     
     
         25 . The device of  claim 24 , wherein said upper surface of said second layer of insulating material is positioned level with or below said upper surface of said sidewall spacer. 
     
     
         26 . A transistor device, comprising:
 a replacement gate structure positioned above a semiconductor substrate, said replacement gate structure having an upper surface;   a sidewall spacer positioned adjacent said replacement gate structure, said sidewall spacer having an upper surface that is positioned at a level that is above a level of said upper surface of said replacement gate structure;   a first layer of insulating material positioned above said substrate adjacent said sidewall spacer, said first layer of insulating material having an upper surface;   a second layer of insulating material positioned on and in contact with said upper surface of said replacement gate structure, said second layer of insulating material having an upper surface;   an etch stop layer positioned on and in contact with said upper surface of said sidewall spacer and on and in contact with said upper surface of said second layer of insulating material, wherein said etch stop layer defines an etch stop recess;   a third layer of insulating material positioned within said etch stop recess and on and in contact with said etch stop layer, said third layer of insulating material having an upper surface that is substantially planar with said upper surface of said first layer of insulating material;   a fourth layer of insulating material positioned above said first layer of insulating material, said third layer of insulating material and said etch stop layer; and   a conductive contact positioned in an opening formed in at least said fourth layer of insulating material and said first layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor.   
     
     
         27 . The device of  claim 26 , wherein said upper surface of said second layer of insulating material is positioned level with or below said upper surface of said sidewall spacer.