Semiconductor Device with a Passivation Layer and Method for Producing Thereof

Abstract

A semiconductor device includes a semiconductor body having a first surface, a contact electrode on the first surface, and a passivation layer on the first surface adjacent the contact electrode and partially overlapping the contact electrode. The passivation layer comprises a layer stack with a first layer comprising an oxide on the first surface, and a second layer comprising a nitride on the first layer.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor body comprising a first surface;   a contact electrode on the first surface; and   a passivation layer on the first surface adjacent the contact electrode and partially overlapping the contact electrode,   wherein the passivation layer comprises a layer stack with a first layer comprising an oxide on the first surface, and a second layer comprising a nitride on the first layer.   
     
     
         2 . The semiconductor device of  claim 1 ,
 wherein a thickness of the first layer is at least 1.5 micrometers, and   wherein a thickness of the second layer is at least 0.6 micrometers.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the semiconductor body comprises at least one of silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), indium gallium arsenide (InGaAs), cadmium telluride (CdTe), cadmium mercury telluride (CdHgTe), and cadmium magnesium telluride (CdMgTe). 
     
     
         4 . The semiconductor device of  claim 1 , wherein the oxide comprises silicon oxide. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the first layer comprises at least one of USG, PSG, BSG, and BPSG. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the nitride comprises silicon nitride. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the layer stack further comprises:
 a third layer comprising an imide on the second layer.   
     
     
         8 . The semiconductor device of  claim 7 , wherein a thickness of the third layer is at least 7 micrometers. 
     
     
         9 . The semiconductor device of  claim 8 ,
 wherein the second layer and the third layer each have an inner edge and an outer edge,   wherein the inner edge of the third layer is distant to the inner edge of the second layer, and   wherein the outer edge of the third layer is distant to the outer edge of the second layer.   
     
     
         10 . The semiconductor device of  claim 7 , further comprising:
 a soft encapsulation layer on the third layer and the contact electrode; and   a housing separated from the third layer by the soft encapsulation layer.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the soft encapsulation layer is selected from the group consisting of
 silicone, and   silica gel.   
     
     
         12 . The semiconductor device of  claim 1 , wherein the contact electrode comprises at least one of aluminum, titanium, copper, an aluminum alloy, and a copper alloy. 
     
     
         13 . The semiconductor device of  claim 1 , further comprising:
 a doped device first region and a doped second device region,   wherein the first doped semiconductor region and the second doped semiconductor region form a pn junction, and   wherein the contact electrode is connected to the second doped semiconductor region.   
     
     
         14 . The semiconductor device of  claim 13 ,
 wherein the pn junction extends to the first surface, and   wherein the passivation layer covers the pn junction on top of the first surface.   
     
     
         15 . The semiconductor device of  claim 14 ,
 wherein the semiconductor device is implemented as a diode, and   wherein the first device region forms a base region and the second device region forms an emitter region of the diode.   
     
     
         16 . The semiconductor device of  claim 14 ,
 wherein the semiconductor device is implemented as an MOS transistor, and   wherein the first device region forms a drift region and the second device region forms a body region of the MOS transistor.   
     
     
         17 . The semiconductor device of  claim 1 , wherein the semiconductor device is implemented as one of a Schottky diode, and a JFET. 
     
     
         18 . The semiconductor device of  claim 1 , further comprising:
 a doped semiconductor region contacted by the contact electrode; and   a Schottky junction between the contact electrode and the doped semiconductor region.   
     
     
         19 . A method of producing a semiconductor device, the method comprising:
 providing a semiconductor body having a first surface;   forming a contact electrode on the first surface; and   forming a passivation layer on the first surface adjacent the contact electrode and partially overlapping the contact electrode,   wherein the passivation layer comprises a layer stack with a first layer comprising an oxide on the first surface, and a second layer comprising a nitride on the first layer.   
     
     
         20 . The method of  claim 19 ,
 wherein the first layer is produced to have a thickness of at least 1.5 micrometers, and   wherein the second layer is produced to have a thickness of at least 0.6 micrometers.   
     
     
         21 . The method of  claim 19 , wherein the semiconductor body ( 100 ) comprises at least one of silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), indium gallium arsenide (InGaAs), cadmium telluride (CdTe), cadmium mercury telluride (CdHgTe), and cadmium magnesium telluride (CdMgTe). 
     
     
         22 . The method of  claim 19 , wherein the oxide comprises silicon oxide. 
     
     
         23 . The semiconductor method of  claim 22 , wherein the first layer comprises at least one of USG, PSG, BSG, and BPSG. 
     
     
         24 . The method of  claim 19 , wherein the nitride comprises silicon nitride. 
     
     
         25 . The method of  claim 19 , further comprising:
 producing a third layer comprising an imide on the second layer.   
     
     
         26 . The method of  claim 25 , wherein producing the first layer and the second layer comprises patterning the first layer and the second layer in an etching process using the third layer as an etch mask. 
     
     
         27 . The method of  claim 25 , wherein the third layer is produced to have a thickness of at least 7 micrometers. 
     
     
         28 . The method of  claim 25 ,
 wherein producing the first layer and the second layer comprises patterning the first layer and the second layer in an etching process using a first etch mask;   wherein producing the third layer comprises removing the first etch mask, depositing a precursor layer and patterning the precursor layer to form the third layer.   
     
     
         29 . The method of  claim 28 , wherein patterning the precursor layer comprises a lithography process. 
     
     
         30 . The method of  claim 28 ,
 wherein the second layer and the third layer each have an inner edge and an outer edge,   and wherein patterning the precursor layer comprises patterning the third layer such the inner edge of the third layer is distant to the inner edge of the second layer and the outer edge of the third layer is distant to the outer edge of the second layer.   
     
     
         31 . The method of  claim 19 , further comprising:
 forming a soft encapsulation layer on the third layer and the contact electrode; and   forming a housing separated from the third layer by the soft encapsulation layer.