Methods of Manufacturing Embedded Bipolar Switching Resistive Memory

Abstract

Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density.

What is claimed is: 
     
         1 . A memory device comprising:
 a bipolar resistive memory element; and   a non-linear response circuit serially coupled with the bipolar resistive memory element,
 wherein the non-linear response circuit comprises two PIN diodes,
 wherein each of the two PIN diodes comprises an undoped intrinsic semiconductor region between a doped p-type semiconductor region and a doped n-type semiconductor region, 
 
 wherein the non-linear response circuit is configured to have a first current gain at first set of voltages and further configure to have a second current gain at second set of voltages, 
 wherein the first current gain is smaller than the second current gain, 
 wherein absolute values of the first set of voltages are smaller than absolute values of the second set of voltages. 
   
     
     
         2 . The memory device of  claim 1 , wherein the two PIN diodes have a same level of reverse current leakage. 
     
     
         3 . The memory device of  claim 2 , wherein the non-linear response circuit has a symmetrical response. 
     
     
         4 . The memory device of  claim 1 , wherein the two PIN diodes have different levels of reverse current leakage. 
     
     
         5 . The memory device of  claim 4 , wherein the non-linear response circuit is asymmetrical. 
     
     
         6 . The memory device of  claim 1 , wherein the two PIN diodes are connected in series back to back in the non-linear response circuit. 
     
     
         7 . The memory device of  claim 1 , wherein the two PIN diodes have an inverse parallel connection in the non-linear response circuit. 
     
     
         8 . The memory device of  claim 1 , wherein the non-linear response circuit reduces a current passing the memory element at an operating voltage. 
     
     
         9 . The memory device of  claim 1 , wherein the non-linear response circuit is further operable as a current limiter for the memory element. 
     
     
         10 . The memory device of  claim 1 , wherein the first set of voltages is ranged from zero to more than half of a first applied voltage or to more than half of a second applied voltage, and wherein the second set of voltages is ranged from less than half of the first applied voltages to the first applied voltage or from less than half of the second applied voltages to the second applied voltage. 
     
     
         11 . The memory device of  claim 1 , wherein the bipolar resistive memory element comprises a non-stoichiometric metal oxide. 
     
     
         12 . The memory device of  claim 11 , wherein the non-stoichiometric metal oxide comprises one of hafnium, zirconium, or aluminum. 
     
     
         13 . The memory device of  claim 11 , wherein the non-stoichiometric metal oxide comprises hafnium. 
     
     
         14 . The memory device of  claim 1 , further comprising a transistor operable as a selector device for the memory element. 
     
     
         15 . The memory device of  claim 14 , wherein the transistor comprises a planar transistor or a vertical transistor. 
     
     
         16 . The memory device of  claim 14 , wherein the transistor comprises a fin planar transistor. 
     
     
         17 . The memory device of  claim 14 , wherein the transistor is coupled to the memory element, and wherein the memory element is coupled to the non-linear response circuit. 
     
     
         18 . The memory device of  claim 14 , wherein the transistor is coupled to the non-linear response circuit, and wherein the non-linear response circuit is coupled to the memory element. 
     
     
         19 . The memory device of  claim 14 , wherein the transistor comprises one of a planar CMOS transistor, a vertical pillar transistor, or a 3D fin-shaped field effect transistor. 
     
     
         20 . The memory device of  claim 14 , wherein the transistor is a finFET device comprising a semiconductor body having a fin-shape formed and formed on a buried oxide layer (BOX).